Digital Electronics a Practical Approach with VHDL 9th Edition by William Kleitz – Ebook PDF Instant Download/Delivery: 0133004489 , 9780133004489
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Product details:
ISBN 10: 0133004489
ISBN 13: 9780133004489
Author: William Kleitz
This is the eBook of the printed book and may not include any media, website access codes, or print supplements that may come packaged with the bound book. Digital Electronics: A Practical Approach with VHDL, Ninth Edition, offers students an easy-to-learn-from resource that emphasizes practical application of circuit design, operation, and troubleshooting. Over 1,000 annotated color figures help explain circuit operation or emphasize critical components and input/output criteria. Throughout the text, the author employs a step-by-step approach that takes students from theory to example to application of the concepts. Over all nine editions, Kleitz has consistently sought out student feedback, along with his own experience of teaching the course in-class and on-line, to improve each new edition.
Digital Electronics a Practical Approach with VHDL 9th Table of contents:
Chapter 1 Number Systems and Codes
Outline
Objectives
Introduction
1–1 Digital versus Analog
1–2 Digital Representations of Analog Quantities
1–3 Decimal Numbering System (Base 10)
1–4 Binary Numbering System (Base 2)
1–5 Decimal-to-Binary Conversion
1–6 Octal Numbering System (Base 8)
1–7 Octal Conversions
1–8 Hexadecimal Numbering System (Base 16)
1–9 Hexadecimal Conversions
1–10 Binary-Coded-Decimal System
1–11 Comparison of Numbering Systems
1–12 The ASCII Code
1–13 Applications of the Numbering Systems
Summary
Glossary
Problems
Schematic Interpretation Problems
MultiSIM® Exercises
Answers to Review Questions
Chapter 2 Digital Electronic Signals and Switches
Outline
Objectives
Introduction
2–1 Digital Signals
2–2 Clock Waveform Timing
2–3 Serial Representation
2–4 Parallel Representation
2–5 Switches in Electronic Circuits
2–6 A Relay as a Switch
2–7 A Diode as a Switch
2–8 A Transistor as a Switch
2–9 The TTL Integrated Circuit
2–10 MultiSIM® Simulation of Switching Circuits
2–11 The CMOS Integrated Circuit
2–12 Surface-Mount Devices
Summary
Glossary
Problems
Schematic Interpretation Problems
MultiSIM® Exercises
Answers to Review Questions
Chapter 3 Basic Logic Gates
Outline
Objectives
Introduction
3–1 The AND Gate
3–2 The OR Gate
3–3 Timing Analysis
3–4 Enable and Disable Functions
3–5 Using IC Logic Gates
3–6 Introduction to Troubleshooting Techniques
3–7 The Inverter
3–8 The NAND Gate
3–9 The NOR Gate
3–10 Logic Gate Waveform Generation
3–11 Using IC Logic Gates
3–12 Summary of the Basic Logic Gates and IEEE/IEC Standard Logic Symbols
Summary
Glossary
Problems
Schematic Interpretation Problems
MultiSIM® Exercises
MultiSIM® Troubleshooting Exercises
Answers to Review Questions
Chapter 4 Programmable Logic Devices: CPLDs and FPGAs with VHDL Design
Outline
Objectives
Introduction
4–1 PLD Design Flow
4–2 PLD Architecture
4–3 Using PLDs to Solve Basic Logic Designs
4–4 Tutorial for Using Altera’s Quartus® II Design and Simulation Software
4–5 FPGA Applications
Summary
Glossary
Problems
FPGA Problems
Chapter 5 Boolean Algebra and Reduction Techniques
Outline
Objectives
Introduction
5–1 Combinational Logic
5–2 Boolean Algebra Laws and Rules
5–3 Simplification of Combinational Logic Circuits Using Boolean Algebra
5–4 Using Quartus® II to Determine Simplified Equations
5–5 De Morgan’s Theorem
5–6 Entering a Truth Table in VHDL Using a Vector Signal
5–7 The Universal Capability of NAND and NOR Gates
5–8 AND–OR–INVERT Gates for Implementing Sum-of-Products Expressions
5–9 Karnaugh Mapping
5–10 System Design Applications
Summary
Glossary
Problems
Schematic Interpretation Problems
MultiSIM® Exercises
MultiSIM® Troubleshooting Exercises
FPGA Problems
Answers to Review Questions
Chapter 6 Exclusive-OR and Exclusive-NOR Gates
Outline
Objectives
Introduction
6–1 The Exclusive-OR Gate
6–2 The Exclusive-NOR Gate
6–3 Parity Generator/Checker
6–4 System Design Applications
6–5 FPGA Design Applications with VHDL
Summary
Glossary
Problems
Schematic Interpretation Problems
MultiSIM® Exercises
FPGA Problems
Answers to Review Questions
Chapter 7 Arithmetic Operations and Circuits
Outline
Objectives
Introduction
7–1 Binary Arithmetic
7–2 Two’s-Complement Representation
7–3 Two’s-Complement Arithmetic
7–4 Hexadecimal Arithmetic
7–5 BCD Arithmetic
7–6 Arithmetic Circuits
7–7 Four-Bit Full-Adder ICs
7–8 VHDL Adders Using Integer Arithmetic
7–9 System Design Applications
7–10 Arithmetic/Logic Units
7–11 FPGA Applications with VHDL and LPMs
Summary
Glossary
Problems
Schematic Interpretation Problems
MultiSIM® Exercises
FPGA Problems
Answers to Review Questions
Chapter 8 Code Converters, Multiplexers, and Demultiplexers
Outline
Objectives
Introduction
8–1 Comparators
8–2 VHDL Comparator Using IF-THEN-ELSE
8–3 Decoding
8–4 Decoders Implemented in the VHDL Language
8–5 Encoding
8–6 Code Converters
8–7 Multiplexers
8–8 Demultiplexers
8–9 System Design Applications
8–10 FPGA Design Applications Using LPMs
Summary
Glossary
Problems
Schematic Interpretation Problems
MultiSIM® Exercises
MultiSIM® Troubleshooting Exercises
FPGA Problems
Answers to Review Questions
Chapter 9 Logic Families and Their Characteristics
Outline
Objectives
Introduction
9–1 The TTL Family
9–2 TTL Voltage and Current Ratings
9–3 Other TTL Considerations
9–4 Improved TTL Series
9–5 The CMOS Family
9–6 Emitter-Coupled Logic
9–7 Comparing Logic Families
9–8 Interfacing Logic Families
9–9 FPGA Electrical Characteristics
Summary
Glossary
Problems
Schematic Interpretation Problems
MultiSIM® Exercises
FPGA Problems
Answers to Review Questions
Chapter 10 Flip-Flops and Registers
Outline
Objectives
Introduction
10–1 S-R Flip-Flop
10–2 Gated S-R Flip-Flop
10–3 Gated D Flip-Flop
10–4 D Latch: 7475 IC; VHDL Description
10–5 D Flip-Flop: 7474 IC; VHDL Description
10–6 Master–Slave J-K Flip-Flop
10–7 Edge-Triggered J-K Flip-Flop with VHDL Model
10–8 Integrated-Circuit J-K Flip-Flop (7476, 74LS76)
10–9 Using an Octal D Flip-Flop in a Microcontroller Application
10–10 Using Altera’s LPM Flip-Flop
Summary
Glossary
Problems
Schematic Interpretation Problems
MultiSIM® Exercises
FPGA Problems
Answers to Review Questions
Chapter 11 Practical Considerations for Digital Design
Outline
Objectives
Introduction
11–1 Flip-Flop Time Parameters
11–2 Automatic Reset
11–3 Schmitt Trigger ICs
11–4 Switch Debouncing
11–5 Sizing Pull-Up Resistors
11–6 Practical Input and Output Considerations
Summary
Glossary
Problems
Schematic Interpretation Problems
MultiSIM® Exercises
FPGA Problems
Answers to Review Questions
Chapter 12 Counter Circuits and VHDL State Machines
Outline
Objectives
Introduction
12–1 Analysis of Sequential Circuits
12–2 Ripple Counters: JK FFs and VHDL Description
12–3 Design of Divide-by-N Counters
12–4 Ripple Counter ICs
12–5 System Design Applications
12–6 Seven-Segment LED Display Decoders: The 7447 IC and VHDL Description
12–7 Synchronous Counters
12–8 Synchronous Up/Down-Counter ICs
12–9 Applications of Synchronous Counter ICs
12–10 VHDL and LPM Counters
12–11 Implementing State Machines in VHDL
Summary
Glossary
Problems
Schematic Interpretation Problems 619
MultiSIM® Exercises
FPGA Problems
Answers to Review Questions
Chapter 13 Shift Registers
Outline
Objectives
Introduction
13–1 Shift Register Basics
13–2 Parallel-to-Serial Conversion
13–3 Recirculating Register
13–4 Serial-to-Parallel Conversion
13–5 Ring Shift Counters and Johnson Shift Counters
13–6 VHDL Description of Shift Registers
13–7 Shift Register ICs
13–8 System Design Applications for Shift Registers
13–9 Driving a Stepper Motor with a Shift Register
13–10 Three-State Buffers, Latches, and Transceivers
13–11 Using the LPM Shift Register and 74194 Macrofunction
13–12 Using VHDL Components and Instantiations
Summary
Glossary
Problems
Schematic Interpretation Problems
MultiSIM® Exercises
FPGA Problems
Answers to Review Questions
Chapter 14 Multivibrators and the 555 Timer
Outline
Objectives
Introduction
14–1 Multivibrators
14–2 Capacitor Charge and Discharge Rates
14–3 Astable Multivibrators
14–4 Monostable Multivibrators
14–5 Integrated-Circuit Monostable Multivibrators
14–6 Retriggerable Monostable Multivibrators
14–7 Astable Operation of the 555 IC Timer
14–8 Monostable Operation of the 555 IC Timer
14–9 Crystal Oscillators
Summary
Glossary
Problems
Schematic Interpretation Problems
MultiSIM® Exercises
Answers to Review Questions
Chapter 15 Interfacing to the Analog World
Outline
Objectives
Introduction
15–1 Digital and Analog Representations
15–2 Operational Amplifier Basics
15–3 Binary-Weighted D/A Converters
15–4 R/2R Ladder D/A Converters
15–5 Integrated-Circuit D/A Converters
15–6 Integrated-Circuit Data Converter Specifications
15–7 Parallel-Encoded A/D Converters
15–8 Counter-Ramp A/D Converters
15–9 Successive-Approximation A/D Conversion
15–10 Integrated-Circuit A/D Converters
15–11 Data Acquisition System Application
15–12 Transducers and Signal Conditioning
Summary
Glossary
Problems
Schematic Interpretation Problems
MultiSIM® Exercises
Answers to Review Questions
Chapter 16 Semiconductor, Magnetic, and Optical Memory
Outline
Objectives
Introduction
16–1 Memory Concepts
16–2 Static RAMs
16–3 Dynamic RAMs
16–4 Read-Only Memories
16–5 Memory Expansion and Address Decoding Applications
16–6 Magnetic and Optical Storage
Summary
Glossary
Problems
Schematic Interpretation Problems
MultiSIM® Exercises
Answers to Review Questions
Chapter 17 Microprocessor Fundamentals
Outline
Objectives
Introduction
17–1 Introduction to System Components and Buses
17–2 Software Control of Microprocessor Systems
17–3 Internal Architecture of a Microprocessor
17–4 Instruction Execution within a Microprocessor
17–5 Hardware Requirements for Basic I/O Programming
17–6 Writing Assembly Language and Machine Language Programs
17–7 Survey of Microprocessors and Manufacturers
Summary of Instructions
Summary
Glossary
Problems
Schematic Interpretation Problems
MultiSIM® Exercises
Answers to Review Questions
Chapter 18 The 8051 Microcontroller
Outline
Objectives
Introduction
18–1 The 8051 Family of Microcontrollers
18–2 8051 Architecture
18–3 Interfacing to External Memory
18–4 The 8051 Instruction Set
18–5 8051 Applications
18–6 Data Acquisition and Control System Application
18–7 Conclusion
Summary
Glossary
Problems
Schematic Interpretation Problems
APPENDIX A: Web Sites
APPENDIX B: Manufacturers’ Data Sheets
APPENDIX C: Explanation of the IEEE/IEC Standard for Logic Symbols (Dependency Notation)
APPENDIX D: Answers to Odd-Numbered Problems
APPENDIX E: VHDL Language Reference
APPENDIX F: Review of Basic Electricity Principles
APPENDIX G: Schematic Diagrams for Chapter-End Problems
APPENDIX H: 8051 Instruction Set Summary
INDEX
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