Computer Architecture A Quantitative Approach 6th editon by John Hennessy, David Patterson – Ebook PDF Instant Download/Delivery: 0128119063, 9780128119068
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ISBN 10: 0128119063
ISBN 13: 9780128119068
Author: John L. Hennessy; David A. Patterson
Computer Architecture: A Quantitative Approach, Sixth Edition has been considered essential reading by instructors, students and practitioners of computer design for over 20 years. The sixth edition of this classic textbook from Hennessy and Patterson, winners of the 2017 ACM A.M. Turing Award recognizing contributions of lasting and major technical importance to the computing field, is fully revised with the latest developments in processor and system architecture. The text now features examples from the RISC-V (RISC Five) instruction set architecture, a modern RISC instruction set developed and designed to be a free and openly adoptable standard. It also includes a new chapter on domain-specific architectures and an updated chapter on warehouse-scale computing that features the first public information on Google’s newest WSC.
True to its original mission of demystifying computer architecture, this edition continues the longstanding tradition of focusing on areas where the most exciting computing innovation is happening, while always keeping an emphasis on good engineering design.
- Winner of a 2019 Textbook Excellence Award (Texty) from the Textbook and Academic Authors Association
- Includes a new chapter on domain-specific architectures, explaining how they are the only path forward for improved performance and energy efficiency given the end of Moore’s Law and Dennard scaling
- Features the first publication of several DSAs from industry
- Features extensive updates to the chapter on warehouse-scale computing, with the first public information on the newest Google WSC
- Offers updates to other chapters including new material dealing with the use of stacked DRAM; data on the performance of new NVIDIA Pascal GPU vs. new AVX-512 Intel Skylake CPU; and extensive additions to content covering multicore architecture and organization
- Includes “Putting It All Together” sections near the end of every chapter, providing real-world technology examples that demonstrate the principles covered in each chapter
- Includes review appendices in the printed text and additional reference appendices available online
- Includes updated and improved case studies and exercises
- ACM named John L. Hennessy and David A. Patterson, recipients of the 2017 ACM A.M. Turing Award for pioneering a systematic, quantitative approach to the design and evaluation of computer architectures with enduring impact on the microprocessor industry
Computer Architecture A Quantitative Approach 6th Table of contents:
1. Fundamentals of Quantitative Design and Analysis
Abstract
1.1 Introduction
1.2 Classes of Computers
1.3 Defining Computer Architecture
1.4 Trends in Technology
1.5 Trends in Power and Energy in Integrated Circuits
1.6 Trends in Cost
1.7 Dependability
1.8 Measuring, Reporting, and Summarizing Performance
1.9 Quantitative Principles of Computer Design
1.10 Putting It All Together: Performance, Price, and Power
1.11 Fallacies and Pitfalls
1.12 Concluding Remarks
1.13 Historical Perspectives and References
Case Studies and Exercises by Diana Franklin
References
2. Memory Hierarchy Design
Abstract
2.1 Introduction
2.2 Memory Technology and Optimizations
2.3 Ten Advanced Optimizations of Cache Performance
2.4 Virtual Memory and Virtual Machines
2.5 Cross-Cutting Issues: The Design of Memory Hierarchies
2.6 Putting It All Together: Memory Hierarchies in the ARM Cortex-A53 and Intel Core i7 6700
2.7 Fallacies and Pitfalls
2.8 Concluding Remarks: Looking Ahead
2.9 Historical Perspectives and References
Case Studies and Exercises by Norman P. Jouppi, Rajeev Balasubramonian, Naveen Muralimanohar, and Sheng Li
References
3. Instruction-Level Parallelism and Its Exploitation
Abstract
3.1 Instruction-Level Parallelism: Concepts and Challenges
3.2 Basic Compiler Techniques for Exposing ILP
3.3 Reducing Branch Costs With Advanced Branch Prediction
3.4 Overcoming Data Hazards With Dynamic Scheduling
3.5 Dynamic Scheduling: Examples and the Algorithm
3.6 Hardware-Based Speculation
3.7 Exploiting ILP Using Multiple Issue and Static Scheduling
3.8 Exploiting ILP Using Dynamic Scheduling, Multiple Issue, and Speculation
3.9 Advanced Techniques for Instruction Delivery and Speculation
3.10 Cross-Cutting Issues
3.11 Multithreading: Exploiting Thread-Level Parallelism to Improve Uniprocessor Throughput
3.12 Putting It All Together: The Intel Core i7 6700 and ARM Cortex-A53
3.13 Fallacies and Pitfalls
3.14 Concluding Remarks: What’s Ahead?
3.15 Historical Perspective and References
Case Studies and Exercises by Jason D. Bakos and Robert P. Colwell
References
4. Data-Level Parallelism in Vector, SIMD, and GPU Architectures
Abstract
4.1 Introduction
4.2 Vector Architecture
4.3 SIMD Instruction Set Extensions for Multimedia
4.4 Graphics Processing Units
4.5 Detecting and Enhancing Loop-Level Parallelism
4.6 Cross-Cutting Issues
4.7 Putting It All Together: Embedded Versus Server GPUs and Tesla Versus Core i7
4.8 Fallacies and Pitfalls
4.9 Concluding Remarks
4.10 Historical Perspective and References
Case Study and Exercises by Jason D. Bakos
References
5. Thread-Level Parallelism
Abstract
5.1 Introduction
5.2 Centralized Shared-Memory Architectures
5.3 Performance of Symmetric Shared-Memory Multiprocessors
5.4 Distributed Shared-Memory and Directory-Based Coherence
5.5 Synchronization: The Basics
5.6 Models of Memory Consistency: An Introduction
5.7 Cross-Cutting Issues
5.8 Putting It All Together: Multicore Processors and Their Performance
5.9 Fallacies and Pitfalls
5.10 The Future of Multicore Scaling
5.11 Concluding Remarks
5.12 Historical Perspectives and References
Case Studies and Exercises by Amr Zaky and David A. Wood
References
6. Warehouse-Scale Computers to Exploit Request-Level and Data-Level Parallelism
Abstract
6.1 Introduction
6.2 Programming Models and Workloads for Warehouse-Scale Computers
6.3 Computer Architecture of Warehouse-Scale Computers
6.4 The Efficiency and Cost of Warehouse-Scale Computers
6.5 Cloud Computing: The Return of Utility Computing
6.6 Cross-Cutting Issues
6.7 Putting It All Together: A Google Warehouse-Scale Computer
6.8 Fallacies and Pitfalls
6.9 Concluding Remarks
6.10 Historical Perspectives and References
Case Studies and Exercises by Parthasarathy Ranganathan
References
7. Domain-Specific Architectures
Abstract
7.1 Introduction
7.2 Guidelines for DSAs
7.3 Example Domain: Deep Neural Networks
7.4 Google’s Tensor Processing Unit, an Inference Data Center Accelerator
7.5 Microsoft Catapult, a Flexible Data Center Accelerator
7.6 Intel Crest, a Data Center Accelerator for Training
7.7 Pixel Visual Core, a Personal Mobile Device Image Processing Unit
7.8 Cross-Cutting Issues
7.9 Putting It All Together: CPUs Versus GPUs Versus DNN Accelerators
7.10 Fallacies and Pitfalls
7.11 Concluding Remarks
7.12 Historical Perspectives and References
Case Studies and Exercises by Cliff Young
References
Appendix A. Instruction Set Principles
Abstract
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