Computer Organization and Architecture Themes and Variations 1st Edition by Alan Clements 1111987041 9781111987046

Part I. The Beginning

Chapter 1. Computer Systems Architecture

1.1. What Is Computer Systems Architecture?

What Is a Computer?

1.2. Architecture and Organization

1.2.1. Computer Systems and Technology

1.2.2. The Role of Computer Architecture in Computer Science

1.3. Development of Computers

1.3.1. Mechanical Computers

1.3.2. Electromechanical Computers

1.3.3. Early Electronic Computers

1.3.4. Minicomputers and the PC Revolution

1.3.5. Moore’s Law and the March of Progress

1.3.6. The March of Memory Technology

1.3.7. Ubiquitous Computing

1.3.8. Multimedia Computers

1.4. The Stored Program Computer

1.4.1. The Problem

1.4.2. The Solution

1.4.3. Constructing an Algorithm

1.4.4. What Does a Computer Need to Solve a Problem?

1.4.5. The Memory

1.5. The Stored Program Concept

Two Address Instructions

1.6. Overview of the Computer System

1.6.1. The Memory Hierarchy

1.6.2. The Bus

1.7. Modern Computing

Summary

Problems

Chapter 2. Computer Arithmetic and Digital Logic

2.1. What is Data?

2.1.1. The Bit and Byte

2.1.2. Bit Patterns

2.2. Numbers

2.2.1. Positional Notation

2.3. Binary Arithmetic

2.4. Signed Integers

2.4.1. Sign and Magnitude Representation

2.4.2. Two’s Complement Arithmetic

2.5. Introduction to Multiplication and Division

2.5.1. Shifting Operations

2.5.2. Unsigned Binary Multiplication

2.5.3. High-Speed Multiplication

2.5.4. Division

2.6. Floating-Point Numbers

Normalization of Floating-Point Numbers

2.6.1. IEEE Floating-Point Numbers

2.7. Floating-Point Arithmetic

Rounding and Truncation Errors

2.8. Floating-Point Arithmetic and the Programmer

2.8.1. Error Propagation in Floating-Point Arithmetic

2.8.2. Generating Mathematical Functions

2.9. Computer Logic

2.9.1. Digital Systems and Gates

2.9.2. Gates

2.9.3. Basic Circuits

2.10. Sequential Circuits

2.10.1. Latches

2.10.2. Registers

2.10.3. Asynchronous Counters

2.10.4. Sequential Circuits

2.11. Buses and Tristate Gates

Registers, Buses, and Functional Units

Summary

Problems

Part II. Instruction Set Architectures

Chapter 3. Architecture and Organization

3.1. Introduction to the Stored Program Machine

3.1.1. Extending the Processor: Dealing with Constants

3.1.2. Extending the Processor: Flow Control

3.2. The Components of an ISA

3.2.1 Registers

3.2.2 Addressing Modes—an Overview

3.2.3. Instruction Formats

3.2.4. Op-codes and Instructions

3.3. ARM Instruction Set Architecture

3.3.1. ARM’s Register Set

3.3.2. ARM’s Instruction Set

3.4. ARM Assembly Language

3.4.1. Structure of an ARM Program

3.4.2. The Assembler – Practical Considerations

3.4.3. Pseudoinstructions

3.5. ARM Data-processing Instructions

3.5.1. Arithmetic Instructions

3.5.2. Bitwise Logical Operations

3.5.3. Shift Operations

3.5.4. Instruction Encoding—An Insight Into the ARM’s Architecture

3.6. ARM’s Flow Control Instructions

3.6.1. Unconditional Branch

3.6.2. Conditional Branch

3.6.3. Compare and Test Instructions

3.6.4. Branching and Loop Constructs

3.6.5. Conditional Execution

3.7. ARM Addressing Modes

3.7.1. Literal Addressing

3.7.2. Register Indirect Addressing

3.7.3. Register Indirect Addressing with an Offset

3.7.4. ARM’s Autoindexing Pre-indexed Addressing Mode

3.7.5. ARM’s Autoindexing Post-Indexing Mode

3.7.6. Program Counter Relative (PC-Relative) Addressing

3.7.7. ARM’s Load and Store Encoding

3.8. Subroutine Call and Return

3.8.1. ARM Support for Subroutines

3.8.2. Conditional Subroutine Calls

3.9. Intermission: Examples of ARM Code

3.9.1. Extracting the Absolute Value

3.9.2. Byte Manipulation and Concatenation

3.9.3. Byte Reversal

3.9.4. Multiplication by 2 n – 1 or 2 n – 1

3.9.5. The Use of Multiple Conditions

3.9.6. With Just One Instruction…

3.9.7. Implementing Multiple Selection

3.9.8. Simple Bit-Level Logical Operations

3.9.9. Hexadecimal Character Conversion

3.9.10. Character Output in Hexadecimal

3.9.11. To Print a Banner

3.10. Subroutines and the Stack

3.10.1. Subroutine Call and Return

3.10.2. Nested Subroutines

3.10.3. Leaf Routines

3.11. Data Size and Arrangement

3.11.1. Data Organization and Endianism

3.11.2. Data Organization and the ARM

3.11.3. Block Move Instructions

3.12. Consolidation—Putting Things Together

Four-Function Calculator Program

Summary

Problems

Chapter 4. Instruction Set Architectures–Breadth and Depth

4.1. The Stack and Data Storage

4.1.1. Storage and the Stack

4.1.2. Passing Parameters via the Stack

4.2. Privileged Modes and Exceptions

4.3. MIPS: Another RISC

MIPS Instruction Format

4.3.1. MIPS Data Processing Instructions

4.4. Data Processing and Data Movement

4.4.1. Indivisible Exchange Instructions

4.4.2. Double-Precision Shifting

4.4.3. Pack and Unpack Instructions

4.4.4. Bounds Testing

4.4.5. Bit Field Data

4.4.6. Mechanizing the Loop

4.5. Memory Indirect Addressing

Using Memory Indirect Addressing to Implement a switch Construct

4.6. Compressed Code, RISC, Thumb, and MIPS16

4.6.1. Thumb ISA

4.6.2. MIPS16

4.7. Variable-Length Instructions

Decoding Variable-Length Instructions

Summary

Problems

Chapter 5. Computer Architecture and Multimedia

5.1. Applications of High-Performance Computing

Computer Graphics

5.1.1. Operations On Images

5.2. Multimedia Influences—Reinventing the CISC

Architectural Progress

5.3. Introduction to SIMD Processing

Packed Operations

5.3.1. Applications of SIMD Technology

5.4. Streaming Extensions and the Development of SIMD Technology

5.4.1. Floating-point Software Extensions

5.4.2. Intel’s Third Layer of Multimedia Extensions

5.4.3. Intel’s SSE3 and SSE4 Instructions

5.4.4. ARM Family Multimedia Instructions

Summary

Problems

Part III. Organization and Efficiency

Chapter 6. Performance—Meaning and Metrics

6.1. Progress and Computer Technology

Moore’s Law

6.2. The Performance of a Computer

6.3. Computer Metrics

6.3.1. Terminology

6.3.2. Clock Rate

6.3.3. MIPS

6.3.4. MFLOPS

6.4. Amdahl’s Law

Examples of the Use of Amdahl’s Law

6.5. Benchmarks

LINPACK and LAPACK

6.6. SPEC

SPEC Methodology

6.7. Averaging Metrics

Geometric Mean

Summary

Problems

Chapter 7. Processor Control

7.1. The Generic Digital Processor

7.1.1. The Microprogram

7.1.2. Generating the Microoperations

7.2. RISC Organization

7.2.1. The Register-to-Register Data Path

7.2.2. Controlling the Single-cycle Flow-through Computer

7.3. Introduction to Pipelining

7.3.1. Speedup Ratio

7.3.2. Implementing Pipelining

7.3.3. Hazards

7.4. Branches and the Branch Penalty

7.4.1. Branch Direction

7.4.2. The Effect of a Branch on the Pipeline

7.4.3. The Cost of Branches

7.4.4. The Delayed Branch

7.5. Branch Prediction

Static and Dynamic Branch Prediction

7.6. Dynamic Branch Prediction

7.6.1. Branch Target Buffer

7.6.2. Two-Level Branch Prediction

Summary

Problems

Chapter 8. Beyond RISC: Superscalar, VLIW, and Itanium

8.1. Superscalar Architecture

Delete

8.1.1. Instruction Level Parallelism (ILP)

8.1.2. Superscalar Instruction Issue

8.1.3. VLIW Processors

8.2. Binary Translation

The IA-32 code

8.2.1. The Transmeta Crusoe

8.3. EPIC Architecture

8.3.1. Itanium Overview

8.3.2. The Itanium Register Set

8.3.3. IA64 Instruction Format

8.3.4. IA64 Instructions and Addressing Modes

8.3.5. Instructions, Bundles, and Breaks

8.3.6. Itanium Organization

8.3.7. Predication

8.3.8. Memory Access and Speculation

8.3.9. The IA64 and Software Pipelining

Summary

Problems

Part IV. The System

Chapter 9. Cache Memory and Virtual Memory

9.1. Introduction to Cache Memory

9.1.1. Structure of Cache Memory

9.2. Performance of Cache Memory

9.3. Cache Organization

9.3.1. Fully Associative Mapped Cache

9.3.2. Direct-Mapped Cache

9.3.3. Set-Associative Cache

9.3.4. Pseudo-Associative, Victim, Annex and Trace Caches

9.4. Considerations in Cache Design

9.4.1. Physical versus Logical Cache

9.4.2. Cache Electronics

9.4.3. Cache Coherency

9.4.4. Line Size

9.4.5. Fetch Policy

9.4.6. Multi-Level Cache Memory

9.4.7. Instruction and Data Caches

9.4.8. Writing to Cache

9.5. Virtual Memory and Memory Management

9.5.1. Memory Management

9.5.2. Virtual Memory

Summary

Problems

Chapter 10. Main Memory

10.1. Introduction

10.1.1. Principles and Parameters of Memory Systems

10.1.2. Memory Hierarchy

10.2. Primary Memory

10.2.1. Static RAM

10.2.2. Interleaved Memory

10.3. DRAM

10.3.1. DRAM Timing

10.3.2. Developments in DRAM Technology

10.4. The Read-Only Memory Family

10.4.1. The EPROM Family

10.5. New and Emerging Nonvolatile Technologies

10.5.1. Ferroelectric Hysteresis

10.5.2. MRAM—Magnetoresistive Random Access Memory

10.5.3. Ovonic Memory

Summary

Problems

Chapter 11. Secondary Storage

11.1. Magnetic Disk Drives

11.2. Magnetism and Data Storage

11.2.1. The Read/Write Head

11.2.2. Limits to Magnetic Recording Density

11.2.3. Principles of Data Recording on Disk

11.3. Data Organization on Disk

11.3.1. Tracks and Sectors

11.3.2. Disk Parameters and Performance

11.3.3. SMART Technology

11.4. Secure Memory and RAID Systems

RAID Level 1

11.5. Solid-State Disk Drives

Special Features of SSDs

11.6. Magnetic Tape

11.7. Optical Storage Technology

11.7.1. Digital Audio

11.7.2. Reading Data from a CD

11.7.3. Low-Level Data Encoding

11.7.4. Recordable Disks

11.7.5. The DVD

11.7.6. Blu-ray

Summary

Problems

Chapter 12. Input/Output

12.1. Fundamental Principles of I/O

Memory-Mapped Peripherals

12.1.1. Peripheral Register Addressing Mechanisms

12.1.2. Peripheral Access and Bus Width

12.2. Data Transfer

12.2.1. Open-Loop Data Transfers

12.2.2. Closed-Loop Data Transfers

12.2.3. Buffering Data

12.3. I/O Strategy

12.3.1. Programmed I/O

12.3.2. Interrupt-driven I/O

12.3.3. Direct Memory Access

12.4. Performance of I/O Systems

12.5. The Bus

12.5.1. Bus Structures and Topologies

12.5.2. The Structure of a Bus

12.6. Arbitrating for the Bus

12.6.1. Localized Arbitration and the VMEbus

12.6.2. Distributed Arbitration

12.7. The PCI and PCIe Buses

12.7.1. The PCI Bus

12.7.2. The PCI Express Bus

12.7.3. CardBus, the PC Card, and ExpressCard

12.8. The SCSI and SAS Interfaces

SCSI Signals

12.9. Serial Interface Buses

12.9.1. The Ethernet

12.9.2. FireWire 1394 Serial Bus

12.9.3. USB

Summary

Problems

Part V. Processor-Level Parallelism

Chapter 13. Processor-Level Parallelism

13.1. Why Parallel Processing?

13.1.1. Power—The Final Frontier

13.2. Performance Revisited

Performance Measurement

13.3. Flynn’s Taxonomy and Multiprocessor Topologies

13.4. Multiprocessor Topologies

13.5. Memory in Multiprocessor Systems

13.5.1. NUMA Architectures

13.5.2. Cache Coherency in Multiprocessor Systems

13.6. Multithreading

13.7. Multi-core Processors

Homogenous and Heterogeneous Processors

13.7.1. Homogeneous Multiprocessors

13.7.2. Heterogeneous Multiprocessors

13.7.3. Networks on a Chip

13.8. Parallel Programming

13.8.1. Parallel Processing and Programming

13.8.2. Message Passing Interface

13.8.3. Partitioned Global Address Space

13.8.4. Synchronization