System Verilog for Design 2nd Edition by Stuart Sutherland , Simon Davidmann , Peter Flake – Ebook PDF Instant Download/Delivery: 0387364957, 978-0387364957
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ISBN 10: 0387364957
ISBN 13: 978-0387364957
Author: Stuart Sutherland , Simon Davidmann , Peter Flake
SystemVerilog is a rich set of extensions to the IEEE 1364-2001 Verilog Hardware Description Language (Verilog HDL). These extensions address two major aspects of HDL-based design. First, modeling very large designs with concise, accurate, and intuitive code. Second, writing high-level test programs to efficiently and effectively verify these large designs.
The first edition of this book addressed the first aspect of the SystemVerilog extensions to Verilog. Important modeling features were presented, such as two-state data types, enumerated types, user-degined types, structures, unions, and interfaces. Emphasis was placed on the proper usage of these enhancements for simulation and synthesis.
SystemVerilog for Design, Second Edition has been extensively revised on a chapter by chapter basis to include the many text and example updates needed to reflect changes that were made between the first edition of this book was written and the finalization of the new standard. It is important that the book reflect these syntax and semantic changes to the SystemVerilog language.
In addition, the second edition features a new chapter that explanis the SystemVerilog “packages”, a new appendix that summarizes the synthesis guidelines presented throughout the book, and all of the code examples have been updated to the final synt
System Verilog for Design 2nd Table of contents:
Introduction to SystemVerilog
SystemVerilog Declaration Spaces
SystemVerilog Literal Values and Built-in Data Types
SystemVerilog User-Defined and Enumerated Types
SystemVerilog Arrays, Structures and Unions
SystemVerilog Procedural Blocks, Tasks and Functions
SystemVerilog Design Hierarchy
SystemVerilog Interfaces
A Complete Design Modeled with SystemVerilog
Behavioral and Transaction Level Modeling
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Tags: Stuart Sutherland, Simon Davidmann, Peter Flake, System Verilog