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ISBN 10: 0321547748
ISBN 13: 978-0321547743
Author: Neil Weste, David Harris
For both introductory and advanced courses in VLSI design, this authoritative, comprehensive textbook is highly accessible to beginners, yet offers unparalleled breadth and depth for more experienced readers.
The Fourth Edition of CMOS VLSI Design: A Circuits and Systems perspective presents broad and in-depth coverage of the entire field of modern CMOS VLSI Design. The authors draw upon extensive industry and classroom experience to introduce today’s most advanced and effective chip design practices. They present extensively updated coverage of every key element of VLSI design, and illuminate the latest design challenges with 65 nm process examples. This book contains unsurpassed circuit-level coverage, as well as a rich set of problems and worked examples that provide deep practical insight to readers at all levels.
CMOS VLSI Design A Circuits and Systems Perspective 4th Table of contents:
Chapter 1 Introduction
1.1 A Brief History
1.2 Preview
1.3 MOS Transistors
1.4 CMOS Logic
1.4.1 The Inverter
1.4.2 The NAND Gate
1.4.3 CMOS Logic Gates
1.4.4 The NOR Gate
1.4.5 Compound Gates
1.4.6 Pass Transistors and Transmission Gates
1.4.7 Tristates
1.4.8 Multiplexers
1.4.9 Sequential Circuits
1.5 CMOS Fabrication and Layout
1.5.1 Inverter Cross-Section
1.5.2 Fabrication Process
1.5.3 Layout Design Rules
1.5.4 Gate Layouts
1.5.5 Stick Diagrams
1.6 Design Partitioning
1.6.1 Design Abstractions
1.6.2 Structured Design
1.6.3 Behavioral, Structural, and Physical Domains
1.7 Example: A Simple MIPS Microprocessor
1.7.1 MIPS Architecture
1.7.2 Multicycle MIPS Microarchitecture
1.8 Logic Design
1.8.1 Top-Level Interfaces
1.8.2 Block Diagrams
1.8.3 Hierarchy
1.8.4 Hardware Description Languages
1.9 Circuit Design
1.10 Physical Design
1.10.1 Floorplanning
1.10.2 Standard Cells
1.10.3 Pitch Matching
1.10.4 Slice Plans
1.10.5 Arrays
1.10.6 Area Estimation
1.11 Design Verification
1.12 Fabrication, Packaging, and Testing
Summary and a Look Ahead
Exercises
Chapter 2 MOS Transistor Theory
2.1 Introduction
2.2 Long-Channel I-V Characteristics
2.3 C-V Characteristics
2.3.1 Simple MOS Capacitance Models
2.3.2 Detailed MOS Gate Capacitance Model
2.3.3 Detailed MOS Diffusion Capacitance Model
2.4 Nonideal I-V Effects
2.4.1 Mobility Degradation and Velocity Saturation
2.4.2 Channel Length Modulation
2.4.3 Threshold Voltage Effects
2.4.4 Leakage
2.4.5 Temperature Dependence
2.4.6 Geometry Dependence
2.4.7 Summary
2.5 DC Transfer Characteristics
2.5.1 Static CMOS Inverter DC Characteristics
2.5.2 Beta Ratio Effects
2.5.3 Noise Margin
2.5.4 Pass Transistor DC Characteristics
2.6 Pitfalls and Fallacies
Summary
Exercises
Chapter 3 CMOS Processing Technology
3.1 Introduction
3.2 CMOS Technologies
3.2.1 Wafer Formation
3.2.2 Photolithography
3.2.3 Well and Channel Formation
3.2.4 Silicon Dioxide (SiO[sup(2)])
3.2.5 Isolation
3.2.6 Gate Oxide
3.2.7 Gate and Source/Drain Formations
3.2.8 Contacts and Metallization
3.2.9 Passivation
3.2.10 Metrology
3.3 Layout Design Rules
3.3.1 Design Rule Background
3.3.2 Scribe Line and Other Structures
3.3.3 MOSIS Scalable CMOS Design Rules
3.3.4 Micron Design Rules
3.4 CMOS Process Enhancements
3.4.1 Transistors
3.4.2 Interconnect
3.4.3 Circuit Elements
3.4.4 Beyond Conventional CMOS
3.5 Technology-Related CAD Issues
3.5.1 Design Rule Checking (DRC)
3.5.2 Circuit Extraction
3.6 Manufacturing Issues
3.6.1 Antenna Rules
3.6.2 Layer Density Rules
3.6.3 Resolution Enhancement Rules
3.6.4 Metal Slotting Rules
3.6.5 Yield Enhancement Guidelines
3.7 Pitfalls and Fallacies
3.8 Historical Perspective
Summary
Exercises
Chapter 4 Delay
4.1 Introduction
4.1.1 Definitions
4.1.2 Timing Optimization
4.2 Transient Response
4.3 RC Delay Model
4.3.1 Effective Resistance
4.3.2 Gate and Diffusion Capacitance
4.3.3 Equivalent RC Circuits
4.3.4 Transient Response
4.3.5 Elmore Delay
4.3.6 Layout Dependence of Capacitance
4.3.7 Determining Effective Resistance
4.4 Linear Delay Model
4.4.1 Logical Effort
4.4.2 Parasitic Delay
4.4.3 Delay in a Logic Gate
4.4.4 Drive
4.4.5 Extracting Logical Effort from Datasheets
4.4.6 Limitations to the Linear Delay Model
4.5 Logical Effort of Paths
4.5.1 Delay in Multistage Logic Networks
4.5.2 Choosing the Best Number of Stages
4.5.3 Example
4.5.4 Summary and Observations
4.5.5 Limitations of Logical Effort
4.5.6 Iterative Solutions for Sizing
4.6 Timing Analysis Delay Models
4.6.1 Slope-Based Linear Model
4.6.2 Nonlinear Delay Model
4.6.3 Current Source Model
4.7 Pitfalls and Fallacies
4.8 Historical Perspective
Summary
Exercises
Chapter 5 Power
5.1 Introduction
5.1.1 Definitions
5.1.2 Examples
5.1.3 Sources of Power Dissipation
5.2 Dynamic Power
5.2.1 Activity Factor
5.2.2 Capacitance
5.2.3 Voltage
5.2.4 Frequency
5.2.5 Short-Circuit Current
5.2.6 Resonant Circuits
5.3 Static Power
5.3.1 Static Power Sources
5.3.2 Power Gating
5.3.3 Multiple Threshold Voltages and Oxide Thicknesses
5.3.4 Variable Threshold Voltages
5.3.5 Input Vector Control
5.4 Energy-Delay Optimization
5.4.1 Minimum Energy
5.4.2 Minimum Energy-Delay Product
5.4.3 Minimum Energy Under a Delay Constraint
5.5 Low Power Architectures
5.5.1 Microarchitecture
5.5.2 Parallelism and Pipelining
5.5.3 Power Management Modes
5.6 Pitfalls and Fallacies
5.7 Historical Perspective
Summary
Exercises
Chapter 6 Interconnect
6.1 Introduction
6.1.1 Wire Geometry
6.1.2 Example: Intel Metal Stacks
6.2 Interconnect Modeling
6.2.1 Resistance
6.2.2 Capacitance
6.2.3 Inductance
6.2.4 Skin Effect
6.2.5 Temperature Dependence
6.3 Interconnect Impact
6.3.1 Delay
6.3.2 Energy
6.3.3 Crosstalk
6.3.4 Inductive Effects
6.3.5 An Aside on Effective Resistance and Elmore Delay
6.4 Interconnect Engineering
6.4.1 Width, Spacing, and Layer
6.4.2 Repeaters
6.4.3 Crosstalk Control
6.4.4 Low-Swing Signaling
6.4.5 Regenerators
6.5 Logical Effort with Wires
6.6 Pitfalls and Fallacies
Summary
Exercises
Chapter 7 Robustness
7.1 Introduction
7.2 Variability
7.2.1 Supply Voltage
7.2.2 Temperature
7.2.3 Process Variation
7.2.4 Design Corners
7.3 Reliability
7.3.1 Reliability Terminology
7.3.2 Oxide Wearout
7.3.3 Interconnect Wearout
7.3.4 Soft Errors
7.3.5 Overvoltage Failure
7.3.6 Latchup
7.4 Scaling
7.4.1 Transistor Scaling
7.4.2 Interconnect Scaling
7.4.3 International Technology Roadmap for Semiconductors
7.4.4 Impacts on Design
7.5 Statistical Analysis of Variability
7.5.1 Properties of Random Variables
7.5.2 Variation Sources
7.5.3 Variation Impacts
7.6 Variation-Tolerant Design
7.6.1 Adaptive Control
7.6.2 Fault Tolerance
7.7 Pitfalls and Fallacies
7.8 Historical Perspective
Summary
Exercises
Chapter 8 Circuit Simulation
8.1 Introduction
8.2 A SPICE Tutorial
8.2.1 Sources and Passive Components
8.2.2 Transistor DC Analysis
8.2.3 Inverter Transient Analysis
8.2.4 Subcircuits and Measurement
8.2.5 Optimization
8.2.6 Other HSPICE Commands
8.3 Device Models
8.3.1 Level 1 Models
8.3.2 Level 2 and 3 Models
8.3.3 BSIM Models
8.3.4 Diffusion Capacitance Models
8.3.5 Design Corners
8.4 Device Characterization
8.4.1 I-V Characteristics
8.4.2 Threshold Voltage
8.4.3 Gate Capacitance
8.4.4 Parasitic Capacitance
8.4.5 Effective Resistance
8.4.6 Comparison of Processes
8.4.7 Process and Environmental Sensitivity
8.5 Circuit Characterization
8.5.1 Path Simulations
8.5.2 DC Transfer Characteristics
8.5.3 Logical Effort
8.5.4 Power and Energy
8.5.5 Simulating Mismatches
8.5.6 Monte Carlo Simulation
8.6 Interconnect Simulation
8.7 Pitfalls and Fallacies
Summary
Exercises
Chapter 9 Combinational Circuit Design
9.1 Introduction
9.2 Circuit Families
9.2.1 Static CMOS
9.2.2 Ratioed Circuits
9.2.3 Cascode Voltage Switch Logic
9.2.4 Dynamic Circuits
9.2.5 Pass-Transistor Circuits
9.3 Circuit Pitfalls
9.3.1 Threshold Drops
9.3.2 Ratio Failures
9.3.3 Leakage
9.3.4 Charge Sharing
9.3.5 Power Supply Noise
9.3.6 Hot Spots
9.3.7 Minority Carrier Injection
9.3.8 Back-Gate Coupling
9.3.9 Diffusion Input Noise Sensitivity
9.3.10 Process Sensitivity
9.3.11 Example: Domino Noise Budgets
9.4 More Circuit Families
9.5 Silicon-On-Insulator Circuit Design
9.5.1 Floating Body Voltage
9.5.2 SOI Advantages
9.5.3 SOI Disadvantages
9.5.4 Implications for Circuit Styles
9.5.5 Summary
9.6 Subthreshold Circuit Design
9.6.1 Sizing
9.6.2 Gate Selection
9.7 Pitfalls and Fallacies
9.8 Historical Perspective
Summary
Exercises
Chapter 10 Sequential Circuit Design
10.1 Introduction
10.2 Sequencing Static Circuits
10.2.1 Sequencing Methods
10.2.2 Max-Delay Constraints
10.2.3 Min-Delay Constraints
10.2.4 Time Borrowing
10.2.5 Clock Skew
10.3 Circuit Design of Latches and Flip-Flops
10.3.1 Conventional CMOS Latches
10.3.2 Conventional CMOS Flip-Flops
10.3.3 Pulsed Latches
10.3.4 Resettable Latches and Flip-Flops
10.3.5 Enabled Latches and Flip-Flops
10.3.6 Incorporating Logic into Latches
10.3.7 Klass Semidynamic Flip-Flop (SDFF)
10.3.8 Differential Flip-Flops
10.3.9 Dual Edge-Triggered Flip-Flops
10.3.10 Radiation-Hardened Flip-Flops
10.3.11 True Single-Phase-Clock (TSPC) Latches and Flip-Flops
10.4 Static Sequencing Element Methodology
10.4.1 Choice of Elements
10.4.2 Characterizing Sequencing Element Delays
10.4.3 State Retention Registers
10.4.4 Level-Converter Flip-Flops
10.4.5 Design Margin and Adaptive Sequential Elements
10.4.6 Two-Phase Timing Types
10.5 Sequencing Dynamic Circuits
10.6 Synchronizers
10.6.1 Metastability
10.6.2 A Simple Synchronizer
10.6.3 Communicating Between Asynchronous Clock Domains
10.6.4 Common Synchronizer Mistakes
10.6.5 Arbiters
10.6.6 Degrees of Synchrony
10.7 Wave Pipelining
10.8 Pitfalls and Fallacies
10.9 Case Study: Pentium 4 and Itanium 2 Sequencing Methodologies
Summary
Exercises
Chapter 11 Datapath Subsystems
11.1 Introduction
11.2 Addition/Subtraction
11.2.1 Single-Bit Addition
11.2.2 Carry-Propagate Addition
11.2.3 Subtraction
11.2.4 Multiple-Input Addition
11.2.5 Flagged Prefix Adders
11.3 One/Zero Detectors
11.4 Comparators
11.4.1 Magnitude Comparator
11.4.2 Equality Comparator
11.4.3 K = A + B Comparator
11.5 Counters
11.5.1 Binary Counters
11.5.2 Fast Binary Counters
11.5.3 Ring and Johnson Counters
11.5.4 Linear-Feedback Shift Registers
11.6 Boolean Logical Operations
11.7 Coding
11.7.1 Parity
11.7.2 Error-Correcting Codes
11.7.3 Gray Codes
11.7.4 XOR/XNOR Circuit Forms
11.8 Shifters
11.8.1 Funnel Shifter
11.8.2 Barrel Shifter
11.8.3 Alternative Shift Functions
11.9 Multiplication
11.9.1 Unsigned Array Multiplication
11.9.2 Two’s Complement Array Multiplication
11.9.3 Booth Encoding
11.9.4 Column Addition
11.9.5 Final Addition
11.9.6 Fused Multiply-Add
11.9.7 Serial Multiplication
11.9.8 Summary
11.10 Parallel-Prefix Computations
11.11 Pitfalls and Fallacies
Summary
Exercises
Chapter 12 Array Subsystems
12.1 Introduction
12.2 SRAM
12.2.1 SRAM Cells
12.2.2 Row Circuitry
12.2.3 Column Circuitry
12.2.4 Multi-Ported SRAM and Register Files
12.2.5 Large SRAMs
12.2.6 Low-Power SRAMs
12.2.7 Area, Delay, and Power of RAMs and Register Files
12.3 DRAM
12.3.1 Subarray Architectures
12.3.2 Column Circuitry
12.3.3 Embedded DRAM
12.4 Read-Only Memory
12.4.1 Programmable ROMs
12.4.2 NAND ROMs
12.4.3 Flash
12.5 Serial Access Memories
12.5.1 Shift Registers
12.5.2 Queues (FIFO, LIFO)
12.6 Content-Addressable Memory
12.7 Programmable Logic Arrays
12.8 Robust Memory Design
12.8.1 Redundancy
12.8.2 Error Correcting Codes (ECC)
12.8.3 Radiation Hardening
12.9 Historical Perspective
Summary
Exercises
Chapter 13 Special-Purpose Subsystems
13.1 Introduction
13.2 Packaging and Cooling
13.2.1 Package Options
13.2.2 Chip-to-Package Connections
13.2.3 Package Parasitics
13.2.4 Heat Dissipation
13.2.5 Temperature Sensors
13.3 Power Distribution
13.3.1 On-Chip Power Distribution Network
13.3.2 IR Drops
13.3.3 L di/dt Noise
13.3.4 On-Chip Bypass Capacitance
13.3.5 Power Network Modeling
13.3.6 Power Supply Filtering
13.3.7 Charge Pumps
13.3.8 Substrate Noise
13.3.9 Energy Scavenging
13.4 Clocks
13.4.1 Definitions
13.4.2 Clock System Architecture
13.4.3 Global Clock Generation
13.4.4 Global Clock Distribution
13.4.5 Local Clock Gaters
13.4.6 Clock Skew Budgets
13.4.7 Adaptive Deskewing
13.5 PLLs and DLLs
13.5.1 PLLs
13.5.2 DLLs
13.5.3 Pitfalls
13.6 I/0
13.6.1 Basic I/O Pad Circuits
13.6.2 Electrostatic Discharge Protection
13.6.3 Example: MOSIS I/O Pads
13.6.4 Mixed-Voltage I/O
13.7 High-Speed Links
13.7.1 High-Speed I/O Channels
13.7.2 Channel Noise and Interference
13.7.3 High-Speed Transmitters and Receivers
13.7.4 Synchronous Data Transmission
13.7.5 Clock Recovery in Source-Synchronous Systems
13.7.6 Clock Recovery in Mesochronous Systems
13.7.7 Clock Recovery in Pleisochronous Systems
13.8 Random Circuits
13.8.1 True Random Number Generators
13.8.2 Chip Identification
13.9 Pitfalls and Fallacies
Summary
Exercises
Chapter 14 Design Methodology and Tools
14.1 Introduction
14.2 Structured Design Strategies
14.2.1 A Software Radio—A System Example
14.2.2 Hierarchy
14.2.3 Regularity
14.2.4 Modularity
14.2.5 Locality
14.2.6 Summary
14.3 Design Methods
14.3.1 Microprocessor/DSP
14.3.2 Programmable Logic
14.3.3 Gate Array and Sea of Gates Design
14.3.4 Cell-Based Design
14.3.5 Full Custom Design
14.3.6 Platform-Based Design—System on a Chip
14.3.7 Summary
14.4 Design Flows
14.4.1 Behavioral Synthesis Design Flow (ASIC Design Flow)
14.4.2 Automated Layout Generation
14.4.3 Mixed-Signal or Custom-Design Flow
14.5 Design Economics
14.5.1 Non-Recurring Engineering Costs (NREs)
14.5.2 Recurring Costs
14.5.3 Fixed Costs
14.5.4 Schedule
14.5.5 Personpower
14.5.6 Project Management
14.5.7 Design Reuse
14.6 Data Sheets and Documentation
14.6.1 The Summary
14.6.2 Pinout
14.6.3 Description of Operation
14.6.4 DC Specifications
14.6.5 AC Specifications
14.6.6 Package Diagram
14.6.7 Principles of Operation Manual
14.6.8 User Manual
14.7 CMOS Physical Design Styles
14.8 Pitfalls and Fallacies
Exercises
Chapter 15 Testing, Debugging, and Verification
15.1 Introduction
15.1.1 Logic Verification
15.1.2 Debugging
15.1.3 Manufacturing Tests
15.2 Testers, Test Fixtures, and Test Programs
15.2.1 Testers and Test Fixtures
15.2.2 Test Programs
15.2.3 Handlers
15.3 Logic Verification Principles
15.3.1 Test Vectors
15.3.2 Testbenches and Harnesses
15.3.3 Regression Testing
15.3.4 Version Control
15.3.5 Bug Tracking
15.4 Silicon Debug Principles
15.5 Manufacturing Test Principles
15.5.1 Fault Models
15.5.2 Observability
15.5.3 Controllability
15.5.4 Repeatability
15.5.5 Survivability
15.5.6 Fault Coverage
15.5.7 Automatic Test Pattern Generation (ATPG)
15.5.8 Delay Fault Testing
15.6 Design for Testability
15.6.1 Ad Hoc Testing
15.6.2 Scan Design
15.6.3 Built-In Self-Test (BIST)
15.6.4 IDDQ Testing
15.6.5 Design for Manufacturability
15.7 Boundary Scan
15.8 Testing in a University Environment
15.9 Pitfalls and Fallacies
Summary
Exercises
Appendix A: Hardware Description Languages
A.1 Introduction
A.1.1 Modules
A.1.2 Simulation and Synthesis
A.2 Combinational Logic
A.2.1 Bitwise Operators
A.2.2 Comments and White Space
A.2.3 Reduction Operators
A.2.4 Conditional Assignment
A.2.5 Internal Variables
A.2.6 Precedence and Other Operators
A.2.7 Numbers
A.2.8 Zs and Xs
A.2.9 Bit Swizzling
A.2.10 Delays
A.3 Structural Modeling
A.4 Sequential Logic
A.4.1 Registers
A.4.2 Resettable Registers
A.4.3 Enabled Registers
A.4.4 Multiple Registers
A.4.5 Latches
A.4.6 Counters
A.4.7 Shift Registers
A.5 Combinational Logic with Always / Process Statements
A.5.1 Case Statements
A.5.2 If Statements
A.5.3 SystemVerilog Casez
A.5.4 Blocking and Nonblocking Assignments
A.6 Finite State Machines
A.6.1 FSM Example
A.6.2 State Enumeration
A.6.3 FSM with Inputs
A.7 Type Idiosyncracies
A.8 Parameterized Modules
A.9 Memory
A.9.1 RAM
A.9.2 Multiported Register Files
A.9.3 ROM
A.10 Testbenches
A.11 SystemVerilog Netlists
A.12 Example: MIPS Processor
A.12.1 Testbench
A.12.2 SystemVerilog
A.12.3 VHDL
Exercises
References
Index
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Tags: Neil Weste, David Harris, CMOS VLSI, Systems Perspective