Design of CMOS Phase Locked Loops From Circuit Level to Architecture Level 1st edition by Behzad Razavi – Ebook PDF Instant Download/Delivery: 1108788866, 9781108788861
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ISBN 10: 1108788866
ISBN 13: 9781108788861
Author: Behzad Razavi
Using a modern, pedagogical approach, this textbook gives students and engineers a comprehensive and rigorous knowledge of CMOS phase-locked loop (PLL) design for a wide range of applications. It features intuitive presentation of theoretical concepts, built up gradually from their simplest form to more practical systems; broad coverage of key topics, including oscillators, phase noise, analog PLLs, digital PLLs, RF synthesizers, delay-locked loops, clock and data recovery circuits, and frequency dividers; tutorial chapters on high-performance oscillator design, covering fundamentals to advanced topologies; and extensive use of circuit simulations to teach design mentality, highlight design flaws, and connect theory with practice. Including over 200 thought-provoking examples highlighting best practices and common pitfalls, 250 end-of-chapter homework problems to test and enhance the readers’ understanding, and solutions and lecture slides for instructors, this is the perfect text for senior undergraduate and graduate-level students and professional engineers who want an in-depth understanding of PLL design.
Design of CMOS Phase Locked Loops From Circuit Level to Architecture Level 1st Table of contents:
1. Oscillator Fundamentals
1.1 Basic Concepts
1.2 Oscillatory Feedback System
1.3 A Deeper Understanding
1.4 Basic Ring Oscillators
1.4.1 Inverter-Based Rings
1.5 Basic LC Oscillators
1.5.1 LC Circuit Concepts
1.5.2 LC Oscillators as Feedback Systems
1.5.3 LC Oscillators as One-Port Systems
1.6 Voltage-Controlled Oscillators
1.7 Appendix I
2. Introduction to Jitter and Phase Noise
2.1 Brief Review of Noise
2.1.1 Noise in Time and Frequency Domains
2.1.2 Device Noise
2.1.3 Propagation of Noise
2.1.4 Average Power of Noise
2.1.5 Approximation of Noise Spectrum
2.1.6 Accumulation of Noise with Time
2.2 Basic Jitter and Phase Noise Concepts
2.2.1 Jitter
2.2.2 Phase Noise
2.2.3 Limitations of Narrowband FM Approximation
2.2.4 Relationship between Jitter and Phase Noise
2.2.5 Types of Jitter
2.3 Trade-Off Between Phase Noise and Power
2.4 Basic Phase Noise Mechanisms
2.4.1 Phase Noise versus Frequency Noise
2.4.2 Ring Oscillators
2.4.3 LC Oscillators
2.5 Effect of Jitter on Performance
2.6 Effect of Phase Noise on Performance
3. Design of Inverter-Based Ring Oscillators
3.1 Phase Noise in Ring Oscillators
3.1.1 General Equation
3.2 Preliminary Design Ideas
3.3 Obtaining the Desired Frequency
3.3.1 Greater Node Capacitances
3.3.2 Greater Number of Stages
3.3.3 Greater Transistor Lengths
3.3.4 Frequency Division
3.4 Phase Noise Considerations
3.4.1 Transistor Noise Simulations
3.4.2 Reference Oscillator Phase Noise
3.4.3 First 2-GHz Oscillator Phase Noise
3.4.4 Second 2-GHz Oscillator Phase Noise
3.4.5 Third 2-GHz Oscillator Phase Noise
3.4.6 Fourth 2-GHz Oscillator Phase Noise
3.5 Frequency Tuning
3.5.1 Tuning Considerations
3.5.2 Continuous and Discrete Tuning
3.5.3 Tuning by Variable Resistance
3.5.4 Tuning by Variable Capacitance
3.6 Discrete Frequency Tuning
3.7 Problem of Supply Noise
3.7.1 Voltage Regulation
3.7.2 Current Regulation
4. Design of Differential and Multiphase Ring Oscillators
4.1 General Considerations
4.2 Phase Noise Considerations
4.3 Basic Differential Ring Design
4.3.1 Initial Design
4.3.2 Design Improvements
4.4 Obtaining the Desired Frequency
4.4.1 Method 1: Greater Node Capacitances
4.4.2 Method 2: Larger Transistors
4.4.3 Method 3: Greater Number of Stages
4.5 Two-Stage Ring Oscillators
4.5.1 Basic Idea
4.5.2 Design Example
4.6 Linear Scaling
4.7 Tuning Techniques
4.7.1 Resistive Tuning
4.7.2 Varactor Tuning
4.7.3 Tuning the Number of Stages
4.8 Comparison of Inverter-Based and Differential Rings
4.9 Inverter-Based Oscillators with Complementary or Quadrature Outputs
4.9.1 Coupled Oscillators
4.9.2 Phase Noise Considerations
4.9.3 Direct Quadrature Generation
4.9.4 Quadrature Generation by Interpolation
4.10 Ring Oscillators with LC Loads
5. LC Oscillator Design
5.1 Inductor Modeling
5.2 Phase Noise Analysis
5.2.1 A Simple Case
5.2.2 Cyclostationary Noise
5.2.3 Noise Injected by Cross-Coupled Pair
5.2.4 Phase Noise Calculation
5.3 Tail Noise
5.3.1 Tail Thermal Noise
5.3.2 Tail Flicker Noise
5.4 Effect of Tail Capacitance
5.5 Step-by-Step Design
5.5.1 Preliminary Thoughts
5.5.2 Design Example
5.5.3 Frequency Tuning
5.5.4 Summary of Oscillator Design Procedure
6. Advanced Oscillator Concepts
6.1 Phase Noise Analysis by Impulse Response
6.1.1 Phase Impulse Response
6.1.2 Effect of Flicker Noise
6.1.3 Cyclostationary Noise
6.2 Current-Limited versus Voltage-Limited Phase Noise
6.3 Oscillators with Complementary Cross-Coupled Pairs
6.3.1 Design Issues
6.3.2 Design Example
6.4 Class-C Oscillators
6.4.1 Design Example
6.5 Phase Noise Reduction by Frequency Division
6.6 Quadrature Generation Techniques
6.6.1 Frequency Division
6.6.2 Quadrature LC Oscillators
7. Basic PLL Architectures
7.1 Phase Detectors
7.2 Phase Control by Feedback
7.3 Analysis of Simple PLL
7.3.1 Static Behavior
7.3.2 Frequency Multiplication
7.3.3 Dynamic Behavior
7.3.4 PLL Transfer Function
7.3.5 Drawbacks of Simple PLL
7.4 Phase/Frequency Detector
7.5 Charge-Pump PLLs
7.5.1 Charge Pumps
7.5.2 PFD/CP/Capacitor Cascade
7.5.3 Basic Charge-Pump PLL
7.5.4 PFD/CP/Capacitor Transfer Function
7.5.5 Phase Margin Calculation
7.6 Higher-Order Loops
7.7 Basic Charge Pump Topologies
7.8 Settling Time
8. PLL Design Considerations
8.1 More on PLL Transfer Functions
8.1.1 Limitations of Continuous-Time Approximation
8.2 PFD Issues
8.3 Charge Pump Issues
8.3.1 Up and Down Skew
8.3.2 Voltage Compliance and Channel-Length Modulation
8.3.3 Random Mismatches
8.3.4 Clock Feedthrough and Charge Injection
8.3.5 Other Charge Pump Nonidealities
8.4 Improved Charge Pumps
8.5 PLLs with Discrete VCO Tuning
8.6 Ripple Reduction by Sampling Filter
8.7 Loop Filter Leakage
8.8 Filter Capacitor Reduction
8.9 Trade-Off Between Bandwidth and Spur Level
8.10 Phase Noise in PLLs
8.10.1 Shaping of Input Phase Noise
8.10.2 Shaping of VCO Phase Noise
8.10.3 Charge Pump Noise
8.10.4 Loop Filter Noise
8.10.5 Supply Noise
9. PLL Design Study
9.1 Design Procedure
9.2 PFD Design
9.3 Charge Pump Design
9.3.1 First CP Design
9.3.2 Second CP Design
9.3.3 Third CP Design
9.3.4 Fourth CP Design
9.3.5 PFD/CP Interface
9.4 Behavioral Simulations of PLL
9.4.1 Loop Simplification
9.4.2 Loop Dynamics
9.4.3 Effect of Ripple
9.5 Simulation of the PLL Transfer Function
9.5.1 One-Pole Approximation
9.5.2 Use of Input FM Source
9.5.3 Use of Random Phase Modulation
9.6 Effect of VCO Phase Noise
9.6.1 VCO Phase Noise Model
9.6.2 VCO Phase Noise Suppression
9.7 Loop Filter Noise
9.8 Doubling the Reference Frequency
9.8.1 Doubler Design
9.8.2 Frequency Doubling Issues
9.8.3 PLL Redesign with Doubled Reference
9.8.4 PLL Simulations
9.9 Feedback Divider Design
9.9.1 Topology Selection
9.9.2 Divider Circuit Design
9.10 Use of Lock Detectors for Calibration
9.11 Design Summary
10. Digital Phase-Locked Loops
10.1 Basic Idea
10.2 ADC Basics
10.2.1 Quantization
10.2.2 Flash ADC
10.2.3 Interpolation
10.3 Time-to-Digital Conversion
10.3.1 Basic TDC Topology
10.3.2 Effect of Quantization Noise
10.3.3 TDC Dynamic Range
10.3.4 TDC Imperfections
10.4 Transistor-Level TDC Design
10.5 Improved TDCs
10.5.1 Vernier TDC
10.5.2 Multi-Path TDCs
10.6 TDC/Oscillator Combinations
10.7 Digitally-Controlled Oscillators
10.7.1 Problem of Discrete Frequencies
10.7.2 DAC Principles
10.7.3 Matrix Architecture
10.7.4 Coarse/Fine DACs
10.7.5 DCO Topologies
10.8 Loop Dynamics
10.8.1 Digital Filter Implementation
10.8.2 Correspondence between Analog and Digital PLLs
11. Delay-Locked Loops
11.1 Basic Idea
11.2 Loop Dynamics
11.3 Choice of Number of Delay Stages
11.4 Effect of Nonidealities
11.4.1 PFD/CP Nonidealities
11.4.2 Supply Noise
11.4.3 Phase Noise
11.5 Generation of Multiple Phases
11.6 Frequency-Multiplying DLLs
11.6.1 Basic Topologies
11.6.2 Design Issues
11.6.3 Use of Frequency Multiplication in False Lock Detection
11.7 DLL/PLL Hybrids
11.8 Phase Interpolation
11.9 High-Speed PD Design
11.10 Duty Cycle Correction
12. RF Synthesis
12.1 RF Synthesis Requirements
12.2 Integer-N Synthesizers
12.3 Fractional-N Synthesizers
12.3.1 The Need for Modulus Randomization
12.3.2 Noise Shaping
12.3.3 Discrete-Time Model
12.3.4 ΔΣ Fractional-N Synthesizers
12.3.5 Higher-Order ΔΣ Modulators
12.4 Nonlinearities in Fractional-N Loops
12.4.1 Charge Pump Nonlinearity
12.4.2 Charge Pump Settling Behavior
12.5 Reduction of Quantization Noise
12.5.1 DAC Feedforward
12.5.2 Noise Cancellation by DTC
12.5.3 Reference Frequency Doubling
13. Clock and Data Recovery Fundamentals
13.1 General Considerations
13.2 Properties of Random Binary Data
13.2.1 Spectrum of NRZ Data
13.3 Clock Recovery by Edge Detection
13.4 Clock Recovery by Phase-Locking
13.4.1 Bang-Bang Phase Detector
13.4.2 Alexander Phase Detector
13.4.3 Hogge Phase Detector
13.5 Problem of Data Swings
14. Advanced Clock and Data Recovery Principles
14.1 Half-Rate Phase Detectors
14.1.1 Half-Rate Bang-Bang PDs
14.1.2 Half-Rate Linear PDs
14.2 Oscillatorless CDR Architectures
14.2.1 DLL-Based CDR Circuits
14.2.2 PI-Based CDR Circuits
14.2.3 Digital CDR Circuits
14.3 Frequency Acquisition
14.4 Jitter Characteristics
14.4.1 Jitter Generation
14.4.2 Jitter Transfer
14.4.3 Jitter Tolerance
15. Frequency Dividers
15.1 General Considerations
15.2 Latch Design Styles
15.2.1 Static Latches
15.2.2 Dynamic Latches
15.3 Divide-by-2 Circuit Design
15.4 Dual-Modulus Prescalers
15.5 Divider Design for RF Synthesis
15.5.1 Pulse Swallow Divider
15.5.2 Vaucher Divider
15.6 Miller Divider
15.7 Injection-Locked Dividers
15.8 Fractional Dividers
15.9 Divider Delay and Phase Noise
Index
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Tags: Behzad Razavi, Architecture Level, Phase Locked, Circuit Level