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Digital Design A Systems Approach 1st edition by William Dally, Curtis Harting ISBN 1108990290 9781108990295

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ISBN 10: 1108990290
ISBN 13: 9781108990295
Author: William Dally, Curtis Harting

This introductory textbook provides students with a system-level perspective and the tools they need to understand, analyze and design digital systems. Going beyond the design of simple combinational and sequential modules, it shows how such modules are used to build complete systems, reflecting real-world digital design. All the essential topics are covered, including design and analysis of combinational and sequential modules, as well as system timing and synchronization. It also teaches how to write Verilog HDL in a productive and maintainable style that enables CAD tools to do much of the tedious work. A complete introduction to digital design is given through clear explanations, extensive examples and online Verilog files. The teaching package is completed with lecture slides, labs and a solutions manual for instructors. Assuming no previous digital knowledge, this textbook is ideal for undergraduate digital design courses that will prepare students for modern digital practice.

Digital Design A Systems Approach 1st Table of contents:

Part I: Introduction

  1. The Digital Abstraction
    1.1. Digital Signals
    1.2. Digital Signals Tolerate Noise
    1.3. Digital Signals Represent Complex Data

    • 1.3.1. Representing the Day of the Year

    • 1.3.2. Representing Subtractive Colors
      1.4. Digital Logic Functions
      1.5. Verilog Description of Digital Circuits and Systems
      1.6. Digital Logic in Systems

    • Summary

    • Bibliographic Notes

    • Exercises

  2. The Practice of Digital System Design
    2.1. The Design Process

    • 2.1.1. Specification

    • 2.1.2. Concept Development and Feasibility

    • 2.1.3. Partitioning and Detailed Design

    • 2.1.4. Verification
      2.2. Digital Systems Are Built from Chips and Boards
      2.3. Computer-Aided Design Tools
      2.4. Moore’s Law and Digital System Evolution

    • Summary

    • Bibliographic Notes

    • Exercises

Part II: Combinational Logic
3. Boolean Algebra
3.1. Axioms
3.2. Properties
3.3. Dual Functions
3.4. Normal Form
3.5. From Equations to Gates
3.6. Boolean Expressions in Verilog

  • Summary

  • Bibliographic Notes

  • Exercises

  1. CMOS Logic Circuits
    4.1. Switch Logic
    4.2. Switch Model of MOS Transistors
    4.3. CMOS Gate Circuits

    • 4.3.1. Basic CMOS Gate Circuit

    • 4.3.2. Inverters, NANDs, and NORs

    • 4.3.3. Complex Gates

    • 4.3.4. Tri-state Circuits

    • 4.3.5. Circuits to Avoid

    • Summary

    • Bibliographic Notes

    • Exercises

  2. Delay and Power of CMOS Circuits
    5.1. Delay of Static CMOS Gates
    5.2. Fan-out and Driving Large Loads
    5.3. Fan-in and Logical Effort
    5.4. Delay Calculation
    5.5. Optimizing Delay
    5.6. Wire Delay
    5.7. Power Dissipation in CMOS Circuits

    • 5.7.1. Dynamic Power

    • 5.7.2. Static Power

    • 5.7.3. Power Scaling

    • Summary

    • Bibliographic Notes

    • Exercises

  3. Combinational Logic Design
    6.1. Combinational Logic
    6.2. Closure
    6.3. Truth Tables, Minterms, and Normal Form
    6.4. Implicants and Cubes
    6.5. Karnaugh Maps
    6.6. Covering a Function
    6.7. From a Cover to Gates
    6.8. Incompletely Specified Functions
    6.9. Product-of-Sums Implementation
    6.10. Hazards

    • Summary

    • Bibliographic Notes

    • Exercises

  4. Verilog Descriptions of Combinational Logic
    7.1. The Prime Number Circuit in Verilog

    • 7.1.1. A Verilog Module

    • 7.1.2. The Case Statement

    • 7.1.3. The Casex Statement

    • 7.1.4. The Assign Statement

    • 7.1.5. Structural Description

    • 7.1.6. The Decimal Prime Number Function
      7.2. A Testbench for the Prime Number Circuit
      7.3. Example: A Seven-Segment Decoder

    • Summary

    • Bibliographic Notes

    • Exercises

  5. Combinational Building Blocks
    8.1. Multi-Bit Notation
    8.2. Decoders
    8.3. Multiplexers
    8.4. Encoders
    8.5. Arbiters and Priority Encoders
    8.6. Comparators
    8.7. Shifters
    8.8. Read-Only Memories
    8.9. Read-Write Memories
    8.10. Programmable Logic Arrays
    8.11. Data Sheets
    8.12. Intellectual Property

    • Summary

    • Bibliographic Notes

    • Exercises

  6. Combinational Examples
    9.1. Multiple-of-3 Circuit
    9.2. Tomorrow Circuit
    9.3. Priority Arbiter
    9.4. Tic-Tac-Toe

    • Summary

    • Exercises

Part III: Arithmetic Circuits
10. Arithmetic Circuits
10.1. Binary Numbers
10.2. Binary Addition
10.3. Negative Numbers and Subtraction
10.4. Multiplication
10.5. Division

  • Summary

  • Exercises

  1. Fixed and Floating-Point Numbers
    11.1. Representation Error: Accuracy, Precision, and Resolution
    11.2. Fixed-Point Numbers

  • 11.2.1. Representation

  • 11.2.2. Operations
    11.3. Floating-Point Numbers

  • 11.3.1. Representation

  • 11.3.2. Denormalized Numbers and Gradual Underflow

  • 11.3.3. Floating-Point Multiplication

  • 11.3.4. Floating-Point Addition/Subtraction

  • Summary

  • Bibliographic Note

  • Exercises

  1. Fast Arithmetic Circuits
    12.1. Carry Look-Ahead
    12.2. Booth Recoding
    12.3. Wallace Trees
    12.4. Synthesis Notes

  • Summary

  • Bibliographic Notes

  • Exercises

  1. Arithmetic Examples
    13.1. Complex Multiplication
    13.2. Converting Between Fixed and Floating-Point Formats

  • 13.2.1. Floating-Point Format

  • 13.2.2. Fixed-to-Floating-Point Conversion

  • 13.2.3. Floating-to-Fixed-Point Conversion
    13.3. FIR Filter

  • Summary

  • Bibliographic Note

  • Exercises

Part IV: Synchronous Sequential Logic
14. Sequential Logic
14.1. Sequential Circuits
14.2. Synchronous Sequential Circuits
14.3. Traffic-Light Controller
14.4. State Assignment
14.5. Implementation of Finite-State Machines
14.6. Verilog Implementation of Finite-State Machines

  • Summary

  • Bibliographic Notes

  • Exercises

  1. Timing Constraints
    15.1. Propagation and Contamination Delay
    15.2. The D Flip-Flop
    15.3. Setup and Hold-Time Constraints
    15.4. The Effect of Clock Skew
    15.5. Timing Examples
    15.6. Timing and Logic Synthesis

  • Summary

  • Bibliographic Notes

  • Exercises

  1. Datapath Sequential Logic
    16.1. Counters

  • 16.1.1. A Simpler Counter

  • 16.1.2. Up/Down/Load Counter

  • 16.1.3. A Timer
    16.2. Shift Registers

  • 16.2.1. A Simple Shift Register

  • 16.2.2. Left/Right/Load (LRL) Shift Register

  • 16.2.3. Universal Shifter/Counter
    16.3. Control and Data Partitioning

  • 16.3.1. Example: Vending Machine FSM

  • 16.3.2. Example: Combination Lock

  • Summary

  • Exercises

  1. Factoring Finite-State Machines
    17.1. A Light Flasher
    17.2. Traffic-Light Controller

  • Summary

  • Exercises

  1. Microcode
    18.1. Simple Microcoded FSM
    18.2. Instruction Sequencing
    18.3. Multi-Way Branches
    18.4. Multiple Instruction Types
    18.5. Microcode Subroutines
    18.6. Simple Computer

  • Summary

  • Bibliographic Notes

  • Exercises

  1. Sequential Examples
    19.1. Divide-by-3 Counter
    19.2. SOS Detector
    19.3. Tic-Tac-Toe Game
    19.4. Huffman Encoder/Decoder

  • 19.4.1. Huffman Encoder

  • 19.4.2. Huffman Decoder

  • Summary

  • Bibliographic Note

  • Exercises

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