Instant download Digital Design A Systems Approach William Dally pdf, docx, kindle format all chapters after payment. 0521199506, 9780521199506
Product details:
ISBN 10: 0521199506
ISBN 13: 9780521199506
Author: Dally; Harting
This introductory textbook provides students with a system-level perspective and the tools they need to understand, analyze and design digital systems. Going beyond the design of simple combinational and sequential modules, it shows how such modules are used to build complete systems, reflecting real-world digital design. All the essential topics are covered, including design and analysis of combinational and sequential modules, as well as system timing and synchronization. It also teaches how to write Verilog HDL in a productive and maintainable style that enables CAD tools to do much of the tedious work. A complete introduction to digital design is given through clear explanations, extensive examples and online Verilog files. The teaching package is completed with lecture slides, labs and a solutions manual for instructors. Assuming no previous digital knowledge, this textbook is ideal for undergraduate digital design courses that will prepare students for modern digital practice.
Table of contents:
Part I Introduction
1 The digital abstraction
1.1 DIGITAL SIGNALS
1.2 DIGITAL SIGNALS TOLERATE NOISE
1.3 DIGITAL SIGNALS REPRESENT COMPLEX DATA
1.3.1 Representing the day of the year
1.3.2 Representing subtractive colors
1.4 DIGITAL LOGIC FUNCTIONS
1.5 VERILOG DESCRIPTION OF DIGITAL CIRCUITS AND SYSTEMS
1.6 DIGITAL LOGIC IN SYSTEMS
Summary
BIBLIOGRAPHIC NOTES
Exercises
2 The practice of digital system design
2.1 THE DESIGN PROCESS
2.1.1 Specification
2.1.2 Concept development and feasibility
2.1.3 Partitioning and detailed design
2.1.4 Verification
2.2 DIGITAL SYSTEMS ARE BUILT FROM CHIPS AND BOARDS
2.3 COMPUTER-AIDED DESIGN TOOLS
2.4 MOORE’S LAW AND DIGITAL SYSTEM EVOLUTION
Summary
BIBLIOGRAPHIC NOTES
Exercises
Part II Combinational logic
3 Boolean algebra
3.1 AXIOMS
3.2 PROPERTIES
3.3 DUAL FUNCTIONS
3.4 NORMAL FORM
3.5 FROM EQUATIONS TO GATES
3.6 BOOLEAN EXPRESSIONS IN VERILOG
Summary
BIBLIOGRAPHIC NOTES
Exercises
4 CMOS logic circuits
4.1 SWITCH LOGIC
4.2 SWITCH MODEL OF MOS TRANSISTORS
4.3 CMOS GATE CIRCUITS
4.3.1 Basic CMOS gate circuit
4.3.2 Inverters, NANDs, and NORs
4.3.3 Complex gates
4.3.4 Tri-state circuits
4.3.5 Circuits to avoid
Summary
BIBLIOGRAPHIC NOTES
Exercises
5 Delay and power of CMOS circuits
5.1 DELAY OF STATIC CMOS GATES
5.2 FAN-OUT AND DRIVING LARGE LOADS
5.3 FAN-IN AND LOGICAL EFFORT
5.4 DELAY CALCULATION
5.5 OPTIMIZING DELAY
5.6 WIRE DELAY
5.7 POWER DISSIPATION IN CMOS CIRCUITS
5.7.1 Dynamic power
5.7.2 Static power
5.7.3 Power scaling
Summary
BIBLIOGRAPHIC NOTES
Exercises
6 Combinational logic design
6.1 COMBINATIONAL LOGIC
6.2 CLOSURE
6.3 TRUTH TABLES, MINTERMS, AND NORMAL FORM
6.4 IMPLICANTS AND CUBES
6.5 KARNAUGH MAPS
6.6 COVERING A FUNCTION
6.7 FROM A COVER TO GATES
6.8 INCOMPLETELY SPECIFIED FUNCTIONS
6.9 PRODUCT-OF-SUMS IMPLEMENTATION
6.10 HAZARDS
Summary
BIBLIOGRAPHIC NOTES
Exercises
7 Verilog descriptions of combinational logic
7.1 THE PRIME NUMBER CIRCUIT IN VERILOG
7.1.1 A Verilog module
7.1.2 The case statement
7.1.3 The casex statement
7.1.4 The assign statement
7.1.5 Structural description
7.1.6 The decimal prime number function
7.2 A TESTBENCH FOR THE PRIME NUMBER CIRCUIT
7.3 EXAMPLE: A SEVEN-SEGMENT DECODER
Summary
BIBLIOGRAPHIC NOTES
Exercises
8 Combinational building blocks
8.1 MULTI-BIT NOTATION
8.2 DECODERS
8.3 MULTIPLEXERS
8.4 ENCODERS
8.5 ARBITERS AND PRIORITY ENCODERS
8.6 COMPARATORS
8.7 SHIFTERS
8.8 READ-ONLY MEMORIES
8.9 READ-WRITE MEMORIES
8.10 PROGRAMMABLE LOGIC ARRAYS
8.11 DATA SHEETS
8.12 INTELLECTUAL PROPERTY
Summary
BIBLIOGRAPHIC NOTES
Exercises
9 Combinational examples
9.1 MULTIPLE-OF-3 CIRCUIT
9.2 TOMORROW CIRCUIT
9.3 PRIORITY ARBITER
9.4 TIC-TAC-TOE
Summary
Exercises
Part III Arithmetic circuits
10 Arithmetic circuits
10.1 BINARY NUMBERS
10.2 BINARY ADDITION
10.3 NEGATIVE NUMBERS AND SUBTRACTION
10.4 MULTIPLICATION
10.5 DIVISION
Summary
Exercises
11 Fixedand floating-point numbers
11.1 REPRESENTATION ERROR: ACCURACY, PRECISION, AND RESOLUTION
11.2 FIXED-POINT NUMBERS
11.2.1 Representation
11.2.2 Operations
11.3 FLOATING-POINT NUMBERS
11.3.1 Representation
11.3.2 Denormalized numbers and gradual underflow
11.3.3 Floating-point multiplication
11.3.4 Floating-point addition/subtraction
Summary
BIBLIOGRAPHIC NOTE
Exercises
12 Fast arithmetic circuits
12.1 CARRY LOOK-AHEAD
12.2 BOOTH RECODING
12.3 WALLACE TREES
12.4 SYNTHESIS NOTES
Summary
BIBLIOGRAPHIC NOTES
Exercises
13 Arithmetic examples
13.1 COMPLEX MULTIPLICATION
13.2 CONVERTING BETWEEN FIXEDAND FLOATING-POINT FORMATS
13.2.1 Floating-point format
13.2.2 Fixedto floating-point conversion
13.2.3 Floatingto fixed-point conversion
13.3 FIR FILTER
Summary
BIBLIOGRAPHIC NOTE
Exercises
Part IV Synchronous sequential logic
14 Sequential logic
14.1 SEQUENTIAL CIRCUITS
14.2 SYNCHRONOUS SEQUENTIAL CIRCUITS
14.3 TRAFFIC-LIGHT CONTROLLER
14.4 STATE ASSIGNMENT
14.5 IMPLEMENTATION OF FINITE-STATE MACHINES
14.6 VERILOG IMPLEMENTATION OF FINITE-STATE MACHINES
Summary
BIBLIOGRAPHIC NOTES
Exercises
15 Timing constraints
15.1 PROPAGATION AND CONTAMINATION DELAY
15.2 THE D FLIP-FLOP
15.3 SETUPAND HOLD-TIME CONSTRAINTS
15.4 THE EFFECT OF CLOCK SKEW
15.5 TIMING EXAMPLES
15.6 TIMING AND LOGIC SYNTHESIS
Summary
BIBLIOGRAPHIC NOTES
Exercises
16 Datapath sequential logic
16.1 COUNTERS
16.1.1 A simpler counter
16.1.2 Up/down/load counter
16.1.3 A timer
16.2 SHIFT REGISTERS
16.2.1 A simple shift register
16.2.2 Left/right/load (LRL) shift register
16.2.3 Universal shifter/counter
16.3 CONTROL AND DATA PARTITIONING
16.3.1 Example: vending machine FSM
16.3.2 Example: combination lock
Summary
Exercises
17 Factoring finite-state machines
17.1 A LIGHT FLASHER
17.2 TRAFFIC-LIGHT CONTROLLER
Summary
Exercises
18 Microcode
18.1 SIMPLE MICROCODED FSM
18.2 INSTRUCTION SEQUENCING
18.3 MULTI-WAY BRANCHES
18.4 MULTIPLE INSTRUCTION TYPES
18.5 MICROCODE SUBROUTINES
18.6 SIMPLE COMPUTER
Summary
BIBLIOGRAPHIC NOTES
Exercises
19 Sequential examples
19.1 DIVIDE-BY-3 COUNTER
19.2 SOS DETECTOR
19.3 TIC-TAC-TOE GAME
19.4 HUFFMAN ENCODER/DECODER
19.4.1 Huffman encoder
19.4.2 Huffman decoder
Summary
BIBLIOGRAPHIC NOTE
Exercises
Part V Practical design
20 Verification and test
20.1 DESIGN VERIFICATION
20.1.1 Verification coverage
20.1.2 Types of tests
20.1.3 Static timing analysis
20.1.4 Formal verification
20.1.5 Bug tracking
20.2 TEST
20.2.1 Fault models
20.2.2 Combinational testing
20.2.3 Testing redundant logic
20.2.4 Scan
20.2.5 Built-in-self-test (BIST)
20.2.6 Characterization
Summary
BIBLIOGRAPHIC NOTES
Exercises
Part VI System design
21 System-level design
21.1 SYSTEM DESIGN PROCESS
21.2 SPECIFICATION
21.2.1 Pong
21.2.2 DES cracker
21.2.3 Music player
21.3 PARTITIONING
21.3.1 Pong
21.3.2 DES cracker
21.3.3 Music synthesizer
Summary
BIBLIOGRAPHIC NOTES
Exercises
22 Interface and system-level timing
22.1 INTERFACE TIMING
22.1.1 Always valid timing
22.1.2 Periodically valid signals
22.1.3 Flow control
22.2 INTERFACE PARTITIONING AND SELECTION
22.3 SERIAL AND PACKETIZED INTERFACES
22.4 ISOCHRONOUS TIMING
22.5 TIMING TABLES
22.5.1 Event flow
22.5.2 Pipelining and anticipatory timing
22.6 INTERFACE AND TIMING EXAMPLES
22.6.1 Pong
22.6.2 DES cracker
22.6.3 Music player
Summary
Exercises
23 Pipelines
23.1 BASIC PIPELINING
23.2 EXAMPLE PIPELINES
23.3 EXAMPLE: PIPELINING A RIPPLE-CARRY ADDER
23.4 PIPELINE STALLS
23.5 DOUBLE BUFFERING
23.6 LOAD BALANCE
23.7 VARIABLE LOADS
23.8 RESOURCE SHARING
Summary
BIBLIOGRAPHIC NOTES
Exercises
24 Interconnect
24.1 ABSTRACT INTERCONNECT
24.2 BUSES
24.3 CROSSBAR SWITCHES
24.4 INTERCONNECTION NETWORKS
Summary
BIBLIOGRAPHIC NOTES
Exercises
25 Memory systems
25.1 MEMORY PRIMITIVES
25.1.1 SRAM arrays
25.1.2 DRAM chips
25.2 BIT-SLICING AND BANKING MEMORY
25.3 INTERLEAVED MEMORY
25.4 CACHES
Summary
BIBLIOGRAPHIC NOTES
Exercises
Part VII Asynchronous logic
26 Asynchronous sequential circuits
26.1 FLOW-TABLE ANALYSIS
26.2 FLOW-TABLE SYNTHESIS: THE TOGGLE CIRCUIT
26.3 RACES AND STATE ASSIGNMENT
Summary
BIBLIOGRAPHIC NOTES
Exercises
27 Flip-flops
27.1 INSIDE A LATCH
27.2 INSIDE A FLIP-FLOP
27.3 CMOS LATCHES AND FLIP-FLOPS
27.4 FLOW-TABLE DERIVATION OF THE LATCH
27.5 FLOW-TABLE SYNTHESIS OF A D-FLIP-FLOP
Summary
BIBLIOGRAPHIC NOTES
Exercises
28 Metastability and synchronization failure
28.1 SYNCHRONIZATION FAILURE
28.2 METASTABILITY
28.3 PROBABILITY OF ENTERING AND LEAVING AN ILLEGAL STATE
28.4 DEMONSTRATION OF METASTABILITY
Summary
BIBLIOGRAPHIC NOTES
Exercises
29 Synchronizer design
29.1 WHERE ARE SYNCHRONIZERS USED?
29.2 BRUTE-FORCE SYNCHRONIZER
29.3 THE PROBLEM WITH MULTI-BIT SIGNALS
29.4 FIFO SYNCHRONIZER
Summary
BIBLIOGRAPHIC NOTES
Exercises
APPENDIX Verilog coding style
A.1 BASIC PRINCIPLES
A.2 ALL STATE SHOULD BE IN EXPLICITLY DECLARED REGISTERS
A.3 DEFINE COMBINATIONAL MODULES SO THEY ARE EASY TO READ
A.4 ASSIGN ALL VARIABLES UNDER ALL CONDITIONS
A.5 KEEP MODULES SMALL
A.6 LARGE MODULES SHOULD BE STRUCTURAL
A.7 USE DESCRIPTIVE SIGNAL NAMES
A.8 USE SYMBOLIC NAMES FOR SUBFIELDS OF SIGNALS
A.9 DEFINE CONSTANTS
A.10 COMMENTS SHOULD DESCRIBE INTENTION AND GIVE RATIONALE, NOT STATE THE OBVIOUS
A.11 NEVER FORGET YOU ARE DEFINING HARDWARE
A.12 READ AND BE A CRITIC OF VERILOG CODE
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