Energy Efficient Embedded Video Processing Systems A Hardware Software Collaborative Approach 1st Edition by Muhammad Usman Karim Khan , Muhammad Shafique , Jörg Henkel ISBN 3319614541 978-3319614540

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ISBN 10:  3319614541
ISBN 13:  978-3319614540
Author:Muhammad Usman Karim Khan , Muhammad Shafique , Jörg Henkel  

This book provides its readers with the means to implement energy-efficient video systems, by using different optimization approaches at multiple abstraction levels.  The authors evaluate the complete video system with a motive to optimize its different software and hardware components in synergy, increase the throughput-per-watt, and address reliability issues. Subsequently, this book provides algorithmic and architectural enhancements, best practices and deployment models for new video systems, while considering new implementation paradigms of hardware accelerators, parallelism for heterogeneous multi- and many-core systems, and systems with long life-cycles. Particular emphasis is given to the current video encoding industry standard H.264/AVC, and one of the latest video encoders (High Efficiency Video Coding, HEVC).

Energy Efficient Embedded Video Processing Systems:  A Hardware-Software Collaborative Approach 1st Table of contents:

Chapter 1: Introduction

1.1 Multimedia Systems

1.1.1 Multimedia Processing Architectures

1.2 Fundamentals of Video Processing

1.2.1 Video Compression

1.3 Design Complexity of a Video System

1.3.1 The Dark Silicon Problem

1.3.2 SRAM Aging

1.4 Video System Design Challenges

1.4.1 Software Layer Challenges

1.4.2 Hardware Layer Challenges

1.5 Limitations of State-of-the-Art

1.6 Design and Optimization Methods Discussed in This Book

1.6.1 Software Layer Design

1.6.1.1 Power-Efficient Resource Budgeting/Parallelization

1.6.1.2 Power-Efficient Software Design

1.6.2 Hardware Layer Design

1.6.2.1 Power-Efficient Accelerator Design

1.6.2.2 Shared Hardware Accelerator Scheduling

1.6.2.3 Memory Subsystem Design

1.6.3 Open-Source Tools

1.7 Book Outline

References

Chapter 2: Background and Related Work

2.1 Overview of Video Processing

2.1.1 Intra- and Inter-frame Processing

2.2 Overview of Video Coding

2.2.1 H.264/AVC and HEVC

2.2.1.1 Intra-prediction Modes

2.2.1.2 HEVC Inter-prediction Modes

2.2.2 Parallelization

2.2.3 DVC and HDVC

2.2.3.1 Distributed Video Coding

2.2.3.2 Hybrid Distributed Video Coding

2.3 Technological Challenges

2.3.1 Dark Silicon or Power Wall

2.3.2 NBTI-Induced SRAM Aging

2.3.3 Other Challenges

2.4 Related Work

2.4.1 Video System Software

2.4.1.1 Parallelization and Workload Balancing

2.4.1.2 Power-Efficient Video Processing Algorithms

2.4.1.3 Mitigating Dark Silicon at Software Level

2.4.2 Video Systems Hardware

2.4.2.1 Efficient Hardware Design and Architectures

2.4.2.2 Memory Subsystem

2.4.2.3 Accelerator Allocation/Scheduling

2.4.2.4 SRAM Aging Rate Reduction Methods

2.4.2.5 Encountering the Power Wall at Hardware Level

2.5 Summary of Related Work

References

Chapter 3: Power-Efficient Video System Design

3.1 System Overview

3.1.1 Design Time Feature Support

3.1.2 Runtime Features and System Dynamics

3.2 Application and Motivational Analysis

3.2.1 Video Application Parallelization

3.2.2 Workload Variations

3.2.3 HEVC Complexity Analysis

3.2.3.1 Texture and PU Size Interdependence

3.2.3.2 Edge Gradients and Intra Angular Modes

3.3 Hardware Platform Analysis

3.3.1 Heterogeneity Among Computing Nodes

3.3.2 Memory Subsystem

3.3.2.1 Analysis of Motion Estimation

3.3.2.2 Hybrid Memories

3.3.3 Analysis of Different Aging Balancing Circuits

3.4 Summary

References

Chapter 4: Energy-Efficient Software Design for Video Systems

4.1 Power-Efficient Application Parallelization

4.1.1 Power-Efficient Workload Balancing

4.2 Compute Configuration

4.2.1 Uniform Tiling

4.2.2 Non-uniform Tiling

4.2.2.1 Evaluation of Non-uniform Tiling

4.2.3 Frequency Estimation (fk,m)

4.2.4 Maximum Workload Estimation (αk,m)

4.2.5 Self-Regulated Frequency Model

4.2.5.1 Frequency Estimation

4.2.5.2 Runtime Frequency Estimation Model Adjustment

4.2.5.3 Core Frequency Allocation per Epoch

4.2.6 Retiling

4.3 Application Configuration

4.3.1 HEVC Application Configurations

4.3.2 HEVC Configuration Tuning

4.3.3 HEVC Parameter Mapping

4.3.3.1 Intra Mode Estimation

4.3.3.2 PU Depth and Size Selection

4.4 Workload Balancing on Heterogeneous Systems

4.4.1 System Model

4.4.2 Load Balancing Algorithm

4.5 Resource Budgeting for Mixed Multithreaded Workloads

4.5.1 Hierarchical Resource Budgeting

4.5.2 Intra-Cluster Power Budgeting pi,j

4.5.3 Inter-Cluster Power Budgeting pi

4.5.4 Selection of Cluster Size

References

Chapter 5: Energy-Efficient Hardware Design for Video Systems

5.1 Custom Video Processing Architectures

5.1.1 Memory Analysis and Video Input

5.1.2 Video Preprocessing

5.1.3 DDR Video Write Master

5.1.4 Heterogeneous Computing Platform

5.2 Accelerator Allocation and Scheduling

5.2.1 Accelerator Sharing on Multi-/Many-Core

5.2.1.1 System Modeling and Objectives

5.2.1.2 Optimization Algorithm

5.2.1.3 Evaluation of Accelerator Allocation

5.2.2 Multicast Video Processing Hardware

5.2.2.1 Video Block Scheduler and Rescheduler

5.3 Efficient Hardware Accelerator Architectures

5.3.1 Low Latency H.264/AVC Encoding Loop

5.3.1.1 4×4 Reordering and HT Lookahead

5.3.1.2 Transform and Quantization Module

5.3.1.3 Prediction Generation and Mode Decision Module

5.3.1.4 Edge-Based Prediction Prioritization

5.3.1.5 Evaluating the H.264/AVC Architecture

5.3.2 Distributed Hardware Accelerator Architecture

5.3.2.1 Energy and Resource Evaluation

5.4 Hybrid Video Memory Architectures

5.4.1 AMBER Memory Hierarchy

5.4.2 NVM Reference Memory Architecture

5.4.3 Energy Management of NVM Reference Memories

5.4.3.1 Memory Access-Based Self-Organizing Map

5.4.4 System Computation Flow

5.5 Energy-Efficient Anti-aging Circuits for SRAM

5.5.1 Memory Write Transducer (MWT)

5.5.2 Aging-Aware Address Generation Unit (AGU)

5.5.3 Aging Controller

5.5.4 Generalization and Applicability

5.5.5 Sensitivity Analysis of SRAM Anti-aging Circuits

References

Chapter 6: Experimental Evaluations and Discussion

6.1 Parallelization and Workload Balancing

6.1.1 Software Architecture and Simulation Setup

6.1.2 Compute and Application Configuration for Uniform Tiling

6.1.3 Compute Configuration with Non-uniform Tiling

6.1.4 Workload Balancing on Heterogeneous Platforms

6.2 Resource Budgeting

6.2.1 Experimental Setup

6.2.2 Results and Discussion

6.3 Memory Subsystem

6.3.1 AMBER: Hybrid Memories

6.3.2 SRAM Anti-aging Circuits

6.3.2.1 Experimental Setup

6.3.2.2 Results and Comparison

6.3.2.3 HCI-Induced Aging

References

Chapter 7: Conclusion and Future Outlook

7.1 Software-Level Techniques

7.2 Hardware-Level Techniques

7.3 Further Improvements

7.3.1 Approximate Computing

7.3.2 GPU-Based Acceleration

7.3.3 Reliability and Workload Management

7.3.4 Generalization

References

Appendices

Appendix A: Pseudo-codes

A.1 Compute and Application Configuration

A.2 Compute Configuration

A.3 PU Map (PUM) Generation for HEVC

A.4 Workload Balancing on Heterogeneous Nodes

A.5 Resource Budgeting for Concurrent Applications

A.6 Cost Function for Hardware Offloading

A.7 Edge Detection for 16×16 MB

A.8 Motion Estimation with Hybrid Memory

Appendix B: ces265 HEVC Video Encoder

B.1 Introduction and Motivation

B.2 Technical Description of ces265

B.3 Implementation and Uses of ces265

B.4 Implementation of Multi-core ces265 on FPGA

B.5. Future Directions

Appendix C: FPGA-Based H.264/AVC Prototype

C.1. Simulation and Design Workflow

C.2. FPGA Prototype

C.3. H.264/AVC Prototype Evaluation

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