FinFET Modeling for IC Simulation and Design Using the BSIM CMG Standard 1st edition by Yogesh Singh Chauhan, Darsen Lu, Sriramkumar Vanugopalan, Sourabh Khandelwal, Juan Pablo Duarte ISBN 0124200852 9780124200852

FinFET Modeling for IC Simulation and Design Using the BSIM CMG Standard 1st edition by Yogesh Singh Chauhan, Darsen Lu, Sriramkumar Vanugopalan, Sourabh Khandelwal, Juan Pablo Duarte – Ebook PDF Instant Download/Delivery: 0124200852 , 9780124200852
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Product details:

ISBN 10: 0124200852
ISBN 13: 9780124200852
Author: Yogesh Singh Chauhan, Darsen Lu, Sriramkumar Vanugopalan, Sourabh Khandelwal, Juan Pablo Duarte

This book is the first to explain FinFET modeling for IC simulation and the industry standard – BSIM-CMG – describing the rush in demand for advancing the technology from planar to 3D architecture, as now enabled by the approved industry standard.

The book gives a strong foundation on the physics and operation of FinFET, details aspects of the BSIM-CMG model such as surface potential, charge and current calculations, and includes a dedicated chapter on parameter extraction procedures, providing a step-by-step approach for the efficient extraction of model parameters.

With this book you will learn:

• Why you should use FinFET
• The physics and operation of FinFET
• Details of the FinFET standard model (BSIM-CMG)
• Parameter extraction in BSIM-CMG
• FinFET circuit design and simulation

• Authored by the lead inventor and developer of FinFET, and developers of the BSIM-CM standard model, providing an experts’ insight into the specifications of the standard
• The first book on the industry-standard FinFET model – BSIM-CMG

FinFET Modeling for IC Simulation and Design Using the BSIM CMG Standard 1st Table of contents:

Chapter 1: FinFET—From device concept to standard compact model

1.1 The root cause of short-channel effects in the twenty-first century MOSFETs

1.2 The thin-body MOSFET concept

1.3 The FinFET and a new scaling path for MOSFETs

1.4 Ultra-thin-body FET

1.5 FinFET compact model—the bridge between FinFET technology and IC design

1.6 A brief history of the first standard compact model, BSIM

1.7 Core and real-device models

1.8 The industry standard FinFET compact model

References

Chapter 2: Compact models for analog and RF applications

2.1 Introduction

2.2 Important Compact Model Metrics

2.3 Analog Metrics

2.3.1 Quiescent Operating Point

2.3.2 Geometric Scalability

2.3.3 Variability Model

2.3.4 Intrinsic Voltage Gain

2.3.5 Speed: Unity Gain Frequency

2.3.6 Noise

2.3.7 Linearity and Symmetry

Harmonic distortion

Gain compression

Memory effects

Intermodulation distortion

2.3.8 Symmetry

2.4 RF Metrics

2.4.1 Two-Port Parameters

2.4.2 The Need for Speed

The maximum unity power gain frequency (fmax)

Mason’s unilateral gain U

2.4.3 Non-Quasi-Static Model

2.4.4 Noise

Minimum achievable noise figure (Fmin)

Simple model for FET noise

Phase noise

Phase noise derivation: Lorentzian spectrum

Phase noise and flicker noise

2.4.5 Linearity

Memory effects

Other distortion metrics

2.5 Conclusion

References

Chapter 3: Core model for FinFETs

3.1 Core Model for Double-Gate FinFETs

3.2 Unified FinFET Compact Model

Chapter 3 Appendix: Explicit surface potential model

3A.1 Continuous Starting Function

3A.2 Quartic Modified Iteration: Implementation and Evaluation

References

Chapter 4: Channel current and real device effects

4.1 Introduction

4.2 Threshold Voltage Roll-Off

4.3 Subthreshold Slope Degradation

4.4 Quantum Mechanical Vth Correction

4.5 Vertical-Field Mobility Degradation

4.6 Drain Saturation Voltage, Vdsat

4.6.1 Extrinsic Case (RDSMOD=1 and 2)

4.6.2 Intrinsic Case (RDSMOD = 0)

4.7 Velocity Saturation Model

4.8 Quantum Mechanical Effects

4.8.1 Effective Width Model

4.8.2 Effective Oxide Thickness/Effective Capacitance

4.8.3 Charge Centroid Calculation for Accumulation

4.9 Lateral Nonuniform Doping Model

4.10 Body Effect Model for a Bulk FinFET (BULKMOD=1)

4.11 Output Resistance Model

4.11.1 Channel-Length Modulation

4.11.2 Drain-Induced Barrier Lowering

4.12 Channel Current

References

Chapter 5: Leakage currents

5.1 Weak-Inversion Current

5.2 Gate-Induced Source and Drain Leakages

5.2.1 GIDL/GISL Current Formulation in BSIM-CMG

5.3 Gate Oxide Tunneling

5.3.1 Gate Oxide Tunneling Formulation in BSIM-CMG

5.3.2 Gate-to-Body Tunneling Current in Depletion/Inversion

5.3.3 Gate-to-Body Tunneling Current in Accumulation

5.3.4 Gate-to-Channel Tunneling Current in Inversion

5.3.5 Gate-to-Source/Drain tunneling Current

5.4 Impact Ionization

References

Chapter 6: Charge, capacitance, and non-quasi-static effects

6.1 Terminal Charges

6.1.1 Gate Charge

6.1.2 Drain Charge

6.1.3 Source Charge

6.2 Transcapacitances

6.3 Non-quasi-Static Effects Models

6.3.1 Relaxation Time Approximation Model

6.3.2 Channel-Induced Gate Resistance Model

6.3.3 Charge Segmentation Model

References

Chapter 7: Parasitic resistances and capacitances

7.1 FinFET Device Structure and Symbol Definitions

7.2 Modeling of Geometry-Dependent Source/Drain Resistances in FinFETs

7.2.1 Contact Resistance

7.2.2 Spreading Resistance

7.2.3 Extension Resistance

7.3 Parasitic Resistance Model Verification

7.3.1 TCAD Simulation Setup

7.3.2 Device Optimization

7.3.3 Extraction of Source and Drain Resistances

7.3.4 Discussion

7.4 Implementation Considerations of the Parasitic Resistance Model

7.4.1 Physical Parameters

7.4.2 Resistance Components

7.5 Gate Electrode Resistance Model

7.6 FinFET Parasitic Capacitance Models

7.6.1 Connection of Parasitic Capacitance Components

7.6.2 Derivation of Two-Dimensional Fringe Capacitance

7.7 Modeling of FinFET Fringe Capacitance in Three Dimensions: CGEOMOD=2

7.8 Parasitic Capacitance Model Verification

7.9 Summary

References

Chapter 8: Noise

8.1 Introduction

8.2 Thermal noise

8.3 Flicker noise

8.4 Other noise components

8.5 Summary

References

Chapter 9: Junction diode I-V and C-V models

9.1 Junction diode current model

9.1.1 Reverse-bias additional leakage model

9.2 Junction diode charge/capacitance model

9.2.1 Reverse-bias model

9.2.2 Forward-bias model

References

Chapter 10: Benchmark tests for compact models

10.1 Asymptotic Correctness

10.2 Benchmark Tests

10.2.1 Tests for Checking Physical Behavior in Weak-Inversion and Strong-Inversion Regions

Slope ratio test

Conductance test

Volume inversion test

10.2.2 Symmetry Tests

Gummel symmetry test

Harmonic balance simulation test

AC symmetry test

10.2.3 Reciprocity Test for Capacitances in a Compact Model

10.2.4 Test for the Self-Heating Effect Model

10.2.5 Tests for the Thermal Noise Model

References

Chapter 11: BSIM-CMG model parameter extraction

11.1 Parameter extraction background

11.2 BSIM-CMG parameter extraction strategy

11.3 Conclusion

References

Chapter 12: Temperature dependence

12.1 Semiconductor properties

12.1.1 Band gap temperature dependence

12.1.2 Temperature dependence of NC, Vbi, and B

12.1.3 Temperature dependence of the intrinsic carrier concentration

12.2 Temperature dependence of the threshold voltage

12.2.1 Temperature dependence of drain-induced barrier lowering

12.2.2 Temperature dependence of the body effect

12.2.3 Subthreshold swing

12.3 Temperature dependence of mobility

12.4 Temperature dependence of velocity saturation

12.4.1 Temperature dependence of the nonsaturation effect

12.5 Temperature dependence of leakage currents

12.5.1 Gate current

12.5.2 Gate-induced drain/source leakage

12.5.3 Impact ionization

12.6 Temperature dependence of parasitic source/drain resistances

12.7 Temperature dependence of source/drain diode characteristics

12.7.1 Direct current model

12.7.2 Capacitance

12.7.3 Trap-assisted tunneling current

12.8 Self-heating effect

12.9 Validation range

12.10 Model validation on measured data

References

Appendix: Parameter List

A.1 Model Controllers

A.2 Instance Parameters

A.3 Process Parameters

A.4 Basic Model Parameters

A.5 Parameters for Geometry-Dependent Parasitics

A.6 Parameters for Temperature Dependence Andself-Heating

A.7 Parameters for Variability Modeling

Index

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Tags: Yogesh Singh Chauhan, Darsen Lu, Sriramkumar Vanugopalan, Sourabh Khandelwal, Juan Pablo Duarte, FinFET Modeling, BSIM CMG