FPGA Prototyping by Systemverilog Examples 2nd edition by Pong P Chu – Ebook PDF Instant Download/Delivery: 1119282709 , 9781119282709
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ISBN 10: 1119282709
ISBN 13: 9781119282709
Author: Pong P Chu
A hands-on introduction to FPGA prototyping and SoC design
This is the successor edition of the popular FPGA Prototyping by Verilog Examples text. It follows the same “learning-by-doing” approach to teach the fundamentals and practices of HDL synthesis and FPGA prototyping. The new edition uses a coherent series of examples to demonstrate the process to develop sophisticated digital circuits and IP (intellectual property) cores, integrate them into an SoC (system on a chip) framework, realize the system on an FPGA prototyping board, and verify the hardware and software operation. The examples start with simple gate-level circuits, progress gradually through the RT (register transfer) level modules, and lead to a functional embedded system with custom I/O peripherals and hardware accelerators. Although it is an introductory text, the examples are developed in a rigorous manner, and the derivations follow the strict design guidelines and coding practices used for large, complex digital systems.
The book is completely updated and uses the SystemVerilog language, which “absorbs” the Verilog language. It presents the hardware design in the SoC context and introduces the hardware-software co-design concept. Instead of treating examples as isolated entities, the book integrates them into a single coherent SoC platform that allows readers to explore both hardware and software “programmability” and develop complex and interesting embedded system projects. The new edition:
- Adds four general-purpose IP cores, which are multi-channel PWM (pulse width modulation) controller, I2C controller, SPI controller, and XADC (Xilinx analog-to-digital converter) controller.
- Introduces a music synthesizer constructed with a DDFS (direct digital frequency synthesis) module and an ADSR (attack-decay-sustain-release) envelope generator.
- Expands the original video controller into a complete stream based video subsystem that incorporates a video synchronization circuit, a test-pattern generator, an OSD (on-screen display) controller, a sprite generator, and a frame buffer.
- Provides a detailed discussion on blocking and nonblocking statements and coding styles.
- Describes basic concepts of software-hardware co-design with Xilinx MicroBlaze MCS soft-core processor.
- Provides an overview of bus interconnect and interface circuit.
- Presents basic embedded system software development.
- Suggests additional modules and peripherals for interesting and challenging projects.
FPGA Prototyping by SystemVerilog Examples makes a natural companion text for introductory and advanced digital design courses and embedded system courses. It also serves as an ideal self-teaching guide for practicing engineers who wish to learn more about this emerging area of interest.
FPGA Prototyping by Systemverilog Examples 2nd Table of contents:
PART I: BASIC DIGITAL CIRCUITS DEVELOPMENT
CHAPTER 1: GATE-LEVEL COMBINATIONAL CIRCUIT
1.1 INTRODUCTION
1.2 GENERAL DESCRIPTION
1.3 BASIC LEXICAL ELEMENTS AND DATA TYPES
1.4 PROGRAM SKELETON
1.5 STRUCTURAL DESCRIPTION
1.6 TOP-LEVEL SIGNAL MAPPING
1.7 TESTBENCH
1.8 BIBLIOGRAPHIC NOTES
1.9 SUGGESTED EXPERIMENTS
Chapter 2: OVERVIEW OF FPGA AND EDA SOFTWARE
2.1 FPGA
2.2 OVERVIEW OF THE DIGILENT NEXYS 4 DDR BOARD
2.3 DEVELOPMENT FLOW
2.4 XILINX VIVADO DESIGN SUITE
2.5 BIBLIOGRAPHIC NOTES
2.6 SUGGESTED EXPERIMENTS
CHAPTER 3: RT-LEVEL COMBINATIONAL CIRCUIT
3.1 OPERATORS
3.2 ALWAYS BLOCK FOR A COMBINATIONAL CIRCUIT
3.3 CODING GUIDELINES
3.4 IF STATEMENT
3.5 CASE STATEMENT
3.6 ROUTING STRUCTURE OF CONDITIONAL CONTROL CONSTRUCTS
3.7 ADDITIONAL CODING GUIDELINES FOR AN ALWAYS BLOCK
3.8 PARAMETER AND CONSTANT
3.9 REPLICATED STRUCTURE
3.10 DESIGN EXAMPLES
3.11 BIBLIOGRAPHIC NOTES
3.12 SUGGESTED EXPERIMENTS
CHAPTER 4: REGULAR SEQUENTIAL CIRCUIT
4.1 INTRODUCTION
4.2 HDL CODE OF THE FF AND REGISTER
4.3 SIMPLE DESIGN EXAMPLES
4.4 TESTBENCH FOR SEQUENTIAL CIRCUITS
4.5 CASE STUDY
4.6 TIMING AND CLOCKING
4.7 BIBLIOGRAPHIC NOTES
4.8 SUGGESTED EXPERIMENTS
CHAPTER 5: FSM
5.1 INTRODUCTION
5.2 FSM CODE DEVELOPMENT
5.3 DESIGN EXAMPLES
5.4 BIBLIOGRAPHIC NOTES
5.5 SUGGESTED EXPERIMENTS
CHAPTER 6: FSMD
6.1 INTRODUCTION
6.2 CODE DEVELOPMENT OF AN FSMD
6.3 DESIGN EXAMPLES
6.4 BIBLIOGRAPHIC NOTES
6.5 SUGGESTED EXPERIMENTS
CHAPTER 7: RAM AND BUFFER OF FPGA
7.1 EMBEDDED MEMORY OF FPGA DEVICE
7.2 GENERAL DESCRIPTION FOR A RAM-LIKE COMPONENT
7.3 FIFO BUFFER
7.4 HDL TEMPLATES FOR MEMORY INFERENCE
7.5 OVERVIEW OF MEMORY CONTROLLER
7.6 BIBLIOGRAPHIC NOTES
7.7 SUGGESTED EXPERIMENTS
CHAPTER 8: SELECTED TOPICS OF SYSTEMVERILOG
8.1 TIMING MODEL
8.2 CODING GUIDELINES REVISITED
8.3 ALTERNATIVE CODING STYLE
8.4 DATA TYPES
8.5 USE OF THE SIGNED DATA TYPE
8.6 BIBLIOGRAPHIC NOTES
8.7 SUGGESTED EXPERIMENTS
PART II: EMBEDDED SOC I: VANILLA FPRO SYSTEM
CHAPTER 9: OVERVIEW OF EMBEDDED SOC SYSTEMS
9.1 EMBEDDED SOC
9.2 DEVELOPMENT FLOW OF THE EMBEDDED SOC
9.3 FPRO SOC PLATFORM
9.4 ADAPTATION ON THE DIGILENT NEXYS 4 DDR BOARD
9.5 PORTABILITY
9.6 ORGANIZATION
9.7 BIBLIOGRAPHIC NOTES
CHAPTER 10: BARE METAL SYSTEM SOFTWARE DEVELOPMENT
10.1 BARE METAL SYSTEM DEVELOPMENT OVERVIEW
10.2 MEMORY-MAPPED I/O
10.3 DIRECT I/O REGISTER ACCESS
10.4 ROBUST I/O REGISTER ACCESS
10.5 TECHNIQUES FOR LOW-LEVEL I/O OPERATIONS
10.6 DEVICE DRIVERS
10.7 FPRO UTILITY ROUTINES AND DIRECTORY STRUCTURE
10.8 TEST PROGRAM
10.9 BIBLIOGRAPHIC NOTES
10.10 SUGGESTED EXPERIMENTS
CHAPTER 11: FPRO BUS PROTOCOL AND MMIO SLOT SPECIFICATION
11.1 FPRO BUS
11.2 INTERFACE WITH THE BUS
11.3 MMIO I/O CORE
11.4 TIMER CORE DEVELOPMENT
11.5 MMIO CONTROLLER
11.6 MCS I/O BUS AND BRIDGE
11.7 VANILLA FPRO SYSTEM CONSTRUCTION
11.8 BIBLIOGRAPHIC NOTES
11.9 SUGGESTED EXPERIMENTS
CHAPTER 12: UART CORE
12.1 INTRODUCTION
12.2 UART CONSTRUCTION
12.3 UART CORE DEVELOPMENT
12.4 UART DRIVER
12.5 ADDITIONAL PROJECT IDEAS
12.6 BIBLIOGRAPHIC NOTES
12.7 SUGGESTED EXPERIMENTS
PART III: EMBEDDED SOC II: BASIC I/O CORES
CHAPTER 13: XILINX XADC CORE
13.1 OVERVIEW OF XADC
13.2 XADC CORE DEVELOPMENT
13.3 XADC CORE DEVICE DRIVER
13.4 SAMPLER FPRO SYSTEM
13.5 ADDITIONAL PROJECT IDEAS
13.6 BIBLIOGRAPHIC NOTES
13.7 SUGGESTED EXPERIMENTS
CHAPTER 14: PULSE WIDTH MODULATION CORE
14.1 INTRODUCTION
14.2 PWM DESIGN
14.3 PWM CORE DEVELOPMENT
14.4 PWM DRIVER
14.5 TESTING
14.6 PROJECT IDEAS
14.7 SUGGESTED EXPERIMENTS
CHAPTER 15: DEBOUNCING CORE AND LED-MUX CORE
15.1 DEBOUNCING CORE
15.2 LED-MUX CORE
15.3 PROJECT IDEAS
15.4 SUGGESTED EXPERIMENTS
CHAPTER 16: SPI CORE
16.1 OVERVIEW
16.2 SPI CONTROLLER
16.3 SPI CORE DEVELOPMENT
16.4 SPI DRIVER
16.5 TEST
16.6 PROJECT IDEAS
16.7 BIBLIOGRAPHIC NOTES
16.8 SUGGESTED EXPERIMENTS
CHAPTER 17: I2C CORE
17.1 OVERVIEW
17.2 I2C CONTROLLER
17.3 I2C CORE DEVELOPMENT
17.4 I2C DRIVER
17.5 TEST
17.6 PROJECT IDEA
17.7 BIBLIOGRAPHIC NOTES
17.8 SUGGESTED EXPERIMENTS
CHAPTER 18: PS2 CORE
18.1 INTRODUCTION
18.2 PS2 CONTROLLER
18.3 PS2 CORE DEVELOPMENT
18.4 PS2 DRIVER
18.5 TEST
18.6 BIBLIOGRAPHIC NOTES
18.7 SUGGESTED EXPERIMENTS
CHAPTER 19: SOUND I: DDFS CORE
19.1 INTRODUCTION
19.2 DESIGN AND IMPLEMENTATION
19.3 FIXED-POINT ARITHMETIC
19.4 DDFS CONSTRUCTION
19.5 DAC (DIGITAL-TO-ANALOG CONVERTER)
19.6 DDFS CORE DEVELOPMENT
19.7 DDFS DRIVER
19.8 TEST
19.9 BIBLIOGRAPHIC NOTES
19.10 SUGGESTED EXPERIMENTS
CHAPTER 20: SOUND II: ADSR CORE
20.1 INTRODUCTION
20.2 ADSR ENVELOPE GENERATOR
20.3 ADSR CORE DEVELOPMENT
20.4 ADSR DRIVER
20.5 TEST
20.6 PROJECT IDEA
20.7 BIBLIOGRAPHIC NOTES
20.8 SUGGESTED EXPERIMENTS
PART IV: EMBEDDED SOC III: VIDEO CORES
CHAPTER 21: INTRODUCTION TO THE VIDEO SYSTEM
21.1 INTRODUCTION TO A VIDEO DISPLAY
21.2 STREAM INTERFACE
21.3 VGA SYNCHRONIZATION
21.4 BAR TEST-PATTERN GENERATOR
21.5 COLOR-TO-GRAYSCALE CONVERSION CIRCUIT
21.6 DEMO VIDEO SYSTEM
21.7 ADVANCED VIDEO STANDARDS
21.8 BIBLIOGRAPHIC NOTES
21.9 SUGGESTED EXPERIMENTS
CHAPTER 22: FPRO VIDEO SUBSYSTEM
22.1 ORGANIZATION OF THE VIDEO SUBSYSTEM
22.2 FPRO VIDEO IP CORE
22.3 EXAMPLE VIDEO CORES
22.4 FPRO VIDEO SYNCHRONIZATION CORE
22.5 DAISY VIDEO SUBSYSTEM
22.6 VANILLA DAISY FPRO SYSTEM
22.7 VIDEO DRIVER AND TEST PROGRAM
22.8 BIBLIOGRAPHIC NOTES
22.9 SUGGESTED EXPERIMENTS
CHAPTER 23: SPRITE CORE
23.1 INTRODUCTION
23.2 BASIC DESIGN
23.3 MOUSE POINTER CORE
23.4 “GHOST” CHARACTER CORE
23.5 SPRITE CORE DRIVER AND TEST PROGRAM
23.6 BIBLIOGRAPHIC NOTES
23.7 SUGGESTED EXPERIMENTS
CHAPTER 24: ON-SCREEN-DISPLAY CORE
24.1 INTRODUCTION TO TILE GRAPHICS
24.2 BASIC OSD DESIGN
24.3 OSD CORE
24.4 OSD CORE DRIVER AND TEST PROGRAM
24.5 BIBLIOGRAPHIC NOTES
24.6 SUGGESTED EXPERIMENTS
CHAPTER 25: VGA FRAME BUFFER CORE
25.1 OVERVIEW
25.2 FRAME BUFFER CORE
25.3 DRIVER AND TEST PROGRAM
25.4 PROJECT IDEAS
25.5 BIBLIOGRAPHIC NOTES
25.6 SUGGESTED EXPERIMENTS
PART V: EPILOGUE
CHAPTER 26: WHAT’S NEXT
REFERENCES
APPENDIX A: TUTORIALS
A.1 OVERVIEW OF XILINX VIVADO IDE
A.2 SHORT TUTORIAL ON VIVADO HARDWARE DEVELOPMENT
A.3 SHORT TUTORIAL ON VIVADO SIMULATION
A.4 TUTORIAL ON IP INSTANTIATION
A.5 SHORT TUTORIAL ON FPRO SYSTEM DEVELOPMENT
A.6 BIBLIOGRAPHIC NOTES
INDEX
EULA
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