Wafer Level 3 D ICs Process Technology 1st edition by Chuan Seng Tan, Ronald Gutmann, Rafael Reif – Ebook PDF Instant Download/Delivery: B00A9YG6QO, 978-0387765341
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ISBN 10: B00A9YG6QO
ISBN 13: 978-0387765341
Author: Chuan Seng Tan, Ronald Gutmann, Rafael Reif
Three-dimensional (3D) integration is clearly the simplest answer to most of the semiconductor industry’s vexing problems: heterogeneous integration and red- tions of power, form factor, delay, and even cost. Conceptually the power, latency, and form factor of a system with a ?xed number of transistors all scale roughly linearly with the diameter of the smallest sphere enclosing frequently interacting devices. This clearly provides the fundamental motivation behind 3D technologies which vertically stack several strata of device and interconnect layers with high vertical interconnectivity. In addition, the ability to vertically stack strata with – vergent and even incompatible process ?ows provides for low cost and low parasitic integration of diverse technologies such as sensors, energy scavengers, nonvolatile memory, dense memory, fast memory, processors, and RF layers. These capabilities coupled with today’s trends of increasing levels of integrated functionality, lower power, smaller form factor, increasingly divergent process ?ows, and functional diversi?cation would seem to make 3D technologies a natural choice for most of the semiconductor industry. Since the concept of vertical integration of different strata has been around for over 20 years, why aren’t vertically stacked strata endemic to the semiconductor industry? The simple answer to this question is that in the past, the 3D advantages while interesting were not necessary due to the tremendous opportunities offered by geometric scaling. In addition, even when the global interconnect problem of high-performance single-core processors seemed insurmountable without inno- tions such as 3D, alternative architectural solutions such as multicores could eff- tivelydelaybutnoteliminatetheneedfor3D.
Wafer Level 3 D ICs Process Technology 1st Table of contents:
1 Overview of Wafer-Level 3D ICs
2 Monolithic 3D Integrated Circuits
3 Stacked CMOS Technologies
4 Wafer-Bonding Technologies and Strategies for 3D ICs
5 Through-Silicon Via Fabrication, Backgrind, and Handle Wafer Technologies
6 Cu Wafer Bonding for 3D IC Applications
7 Cu/Sn Solid–Liquid Interdiffusion Bonding
8 An SOI-Based 3D Circuit Integration Technology
9 3D Fabrication Options for High-Performance CMOS Technology
10 3D Integration Based upon Dielectric Adhesive Bonding
11 Direct Hybrid Bonding
12 3D Memory
13 Circuit Architectures for 3D Integration
14 Thermal Challenges of 3D ICs
15 Status and Outlook
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Tags: Chuan Seng Tan, Ronald Gutmann, Rafael Reif, Level 3, Process Technology